Lines Matching refs:IS_CHERRYVIEW
275 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) in intel_update_czclk()
3094 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in valleyview_crtc_enable()
3107 if (IS_CHERRYVIEW(dev_priv)) in valleyview_crtc_enable()
3218 if (IS_CHERRYVIEW(dev_priv)) in i9xx_crtc_disable()
3776 return DISPLAY_VER(dev_priv) == 7 || IS_CHERRYVIEW(dev_priv); in transcoder_has_m2_n2()
4007 IS_CHERRYVIEW(dev_priv)) { in i9xx_set_pipeconf()
4039 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_set_pipeconf()
4212 IS_CHERRYVIEW(dev_priv)) { in i9xx_get_pipe_config()
4228 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_get_pipe_config()
4235 if (IS_CHERRYVIEW(dev_priv)) in i9xx_get_pipe_config()
4252 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) in i9xx_get_pipe_config()
4274 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { in i9xx_get_pipe_config()
4286 if (IS_CHERRYVIEW(dev_priv)) in i9xx_get_pipe_config()
6534 IS_CHERRYVIEW(dev_priv))) in compute_baseline_pipe_bpp()
6831 if (IS_CHERRYVIEW(dev_priv)) in intel_dump_pipe_config()
7049 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_crtc_prepare_cleared_state()
7384 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in fastboot_enabled()
7662 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_pipe_config_compare()
7704 if (IS_CHERRYVIEW(dev_priv)) in intel_pipe_config_compare()
8568 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || in active_planes_affects_min_cdclk()
10331 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_setup_outputs()
10366 if (IS_CHERRYVIEW(dev_priv)) { in intel_setup_outputs()
10653 } else if (IS_CHERRYVIEW(dev_priv) || in intel_init_display_hooks()
11899 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_modeset_setup_hw_state()