Lines Matching refs:IS_HASWELL
1714 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) in ilk_pfit_enable()
1818 if (IS_HASWELL(dev_priv) && in hsw_pre_update_disable_ips()
1845 if (IS_HASWELL(dev_priv) && in hsw_post_update_enable_ips()
1923 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915)); in needs_async_flip_vtd_wa()
2730 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { in hsw_crtc_enable()
3769 if (IS_HASWELL(dev_priv)) in transcoder_has_m2_n2()
3898 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && in intel_set_transcoder_timings()
3927 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_pipe_is_interlaced()
4781 if (IS_HASWELL(dev_priv) && crtc_state->dither) in hsw_set_transconf()
4789 if (IS_HASWELL(dev_priv) && in hsw_set_transconf()
5463 if (IS_HASWELL(dev_priv)) { in hsw_get_pipe_config()
5498 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in hsw_get_pipe_config()
5511 if (IS_HASWELL(dev_priv)) in hsw_get_pipe_config()
6434 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { in intel_crtc_atomic_check()
7661 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || in intel_pipe_config_compare()
8497 if (IS_HASWELL(dev_priv)) in intel_modeset_checks()
8567 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || in active_planes_affects_min_cdclk()
9320 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_pipe_fastset()
10490 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { in intel_mode_valid()
11277 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { in intel_sanitize_frame_start_delay()
11762 if (IS_HASWELL(dev_priv)) { in intel_early_display_was()