Lines Matching refs:PIPE_A
639 assert_fdi_rx_enabled(dev_priv, PIPE_A); in lpt_enable_pch_transcoder()
641 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); in lpt_enable_pch_transcoder()
647 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); in lpt_enable_pch_transcoder()
708 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); in lpt_disable_pch_transcoder()
710 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); in lpt_disable_pch_transcoder()
718 return PIPE_A; in intel_crtc_pch_transcoder()
1670 assert_pch_transcoder_disabled(dev_priv, PIPE_A); in lpt_pch_enable()
1675 ilk_pch_transcoder_set_timings(crtc_state, PIPE_A); in lpt_pch_enable()
2529 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; in hsw_crtc_supports_ips()
3470 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); in intel_crtc_supports_double_wide()
4252 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) in i9xx_get_pipe_config()
5236 trans_pipe = PIPE_A; in hsw_enabled_transcoders()
5408 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); in hsw_get_ddi_port_state()
11199 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE); in i830_disable_pipe()
11267 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A); in has_pch_trancoder()
11484 enum pipe pipe = PIPE_A; in readout_plane_state()
11787 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A)) in ibx_sanitize_pch_hdmi_port()
11795 val |= SDVO_PIPE_SEL(PIPE_A); in ibx_sanitize_pch_hdmi_port()
11806 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A)) in ibx_sanitize_pch_dp_port()
11814 val |= DP_PIPE_SEL(PIPE_A); in ibx_sanitize_pch_dp_port()