Lines Matching refs:pipe_mode
3475 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; in ilk_pipe_pixel_rate()
3522 crtc_state->hw.pipe_mode.crtc_clock; in intel_crtc_compute_pixel_rate()
3531 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; in intel_crtc_readout_derived_state() local
3534 drm_mode_copy(pipe_mode, adjusted_mode); in intel_crtc_readout_derived_state()
3541 pipe_mode->crtc_hdisplay /= 2; in intel_crtc_readout_derived_state()
3542 pipe_mode->crtc_hblank_start /= 2; in intel_crtc_readout_derived_state()
3543 pipe_mode->crtc_hblank_end /= 2; in intel_crtc_readout_derived_state()
3544 pipe_mode->crtc_hsync_start /= 2; in intel_crtc_readout_derived_state()
3545 pipe_mode->crtc_hsync_end /= 2; in intel_crtc_readout_derived_state()
3546 pipe_mode->crtc_htotal /= 2; in intel_crtc_readout_derived_state()
3547 pipe_mode->crtc_clock /= 2; in intel_crtc_readout_derived_state()
3560 pipe_mode->crtc_hdisplay = (pipe_mode->crtc_hdisplay - overlap) * n; in intel_crtc_readout_derived_state()
3561 pipe_mode->crtc_hblank_start = (pipe_mode->crtc_hblank_start - overlap) * n; in intel_crtc_readout_derived_state()
3562 pipe_mode->crtc_hblank_end = (pipe_mode->crtc_hblank_end - overlap) * n; in intel_crtc_readout_derived_state()
3563 pipe_mode->crtc_hsync_start = (pipe_mode->crtc_hsync_start - overlap) * n; in intel_crtc_readout_derived_state()
3564 pipe_mode->crtc_hsync_end = (pipe_mode->crtc_hsync_end - overlap) * n; in intel_crtc_readout_derived_state()
3565 pipe_mode->crtc_htotal = (pipe_mode->crtc_htotal - overlap) * n; in intel_crtc_readout_derived_state()
3566 pipe_mode->crtc_clock *= n; in intel_crtc_readout_derived_state()
3568 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); in intel_crtc_readout_derived_state()
3569 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); in intel_crtc_readout_derived_state()
3571 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); in intel_crtc_readout_derived_state()
3594 struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode; in intel_crtc_compute_config() local
3597 drm_mode_copy(pipe_mode, &pipe_config->hw.adjusted_mode); in intel_crtc_compute_config()
3601 pipe_mode->crtc_clock /= 2; in intel_crtc_compute_config()
3602 pipe_mode->crtc_hdisplay /= 2; in intel_crtc_compute_config()
3603 pipe_mode->crtc_hblank_start /= 2; in intel_crtc_compute_config()
3604 pipe_mode->crtc_hblank_end /= 2; in intel_crtc_compute_config()
3605 pipe_mode->crtc_hsync_start /= 2; in intel_crtc_compute_config()
3606 pipe_mode->crtc_hsync_end /= 2; in intel_crtc_compute_config()
3607 pipe_mode->crtc_htotal /= 2; in intel_crtc_compute_config()
3615 pipe_mode->crtc_hdisplay = (pipe_mode->crtc_hdisplay - overlap) * n; in intel_crtc_compute_config()
3616 pipe_mode->crtc_hblank_start = (pipe_mode->crtc_hblank_start - overlap) * n; in intel_crtc_compute_config()
3617 pipe_mode->crtc_hblank_end = (pipe_mode->crtc_hblank_end - overlap) * n; in intel_crtc_compute_config()
3618 pipe_mode->crtc_hsync_start = (pipe_mode->crtc_hsync_start - overlap) * n; in intel_crtc_compute_config()
3619 pipe_mode->crtc_hsync_end = (pipe_mode->crtc_hsync_end - overlap) * n; in intel_crtc_compute_config()
3620 pipe_mode->crtc_htotal = (pipe_mode->crtc_htotal - overlap) * n; in intel_crtc_compute_config()
3621 pipe_mode->crtc_clock *= n; in intel_crtc_compute_config()
3624 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); in intel_crtc_compute_config()
3634 pipe_mode->crtc_clock > clock_limit) { in intel_crtc_compute_config()
3640 if (pipe_mode->crtc_clock > clock_limit) { in intel_crtc_compute_config()
3643 pipe_mode->crtc_clock, clock_limit, in intel_crtc_compute_config()
6283 const struct drm_display_mode *pipe_mode = in hsw_linetime_wm() local
6284 &crtc_state->hw.pipe_mode; in hsw_linetime_wm()
6290 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, in hsw_linetime_wm()
6291 pipe_mode->crtc_clock); in hsw_linetime_wm()
6299 const struct drm_display_mode *pipe_mode = in hsw_ips_linetime_wm() local
6300 &crtc_state->hw.pipe_mode; in hsw_ips_linetime_wm()
6306 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, in hsw_ips_linetime_wm()
6316 const struct drm_display_mode *pipe_mode = in skl_linetime_wm() local
6317 &crtc_state->hw.pipe_mode; in skl_linetime_wm()
6323 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, in skl_linetime_wm()
6795 drm_mode_debug_printmodeline(&pipe_config->hw.pipe_mode); in intel_dump_pipe_config()
6796 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode); in intel_dump_pipe_config()
7005 crtc_state->hw.pipe_mode = from_crtc_state->hw.pipe_mode; in copy_bigjoiner_crtc_state()
7614 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay); in intel_pipe_config_compare()
7615 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal); in intel_pipe_config_compare()
7616 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_start); in intel_pipe_config_compare()
7617 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_end); in intel_pipe_config_compare()
7618 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_start); in intel_pipe_config_compare()
7619 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_end); in intel_pipe_config_compare()
7621 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay); in intel_pipe_config_compare()
7622 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal); in intel_pipe_config_compare()
7623 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_start); in intel_pipe_config_compare()
7624 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_end); in intel_pipe_config_compare()
7625 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_start); in intel_pipe_config_compare()
7626 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_end); in intel_pipe_config_compare()
7773 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock); in intel_pipe_config_compare()