Lines Matching refs:cfgcr1
1128 i915_reg_t ctl, cfgcr1, cfgcr2; member
1141 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
1147 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
1153 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
1183 intel_de_write(dev_priv, regs[id].cfgcr1, pll->state.hw_state.cfgcr1); in skl_ddi_pll_enable()
1185 intel_de_posting_read(dev_priv, regs[id].cfgcr1); in skl_ddi_pll_enable()
1245 hw_state->cfgcr1 = intel_de_read(dev_priv, regs[id].cfgcr1); in skl_ddi_pll_get_hw_state()
1540 u32 ctrl1, cfgcr1, cfgcr2; in skl_ddi_hdmi_pll_dividers() local
1556 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE | in skl_ddi_hdmi_pll_dividers()
1570 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; in skl_ddi_hdmi_pll_dividers()
1634 dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) * in skl_ddi_wrpll_get_freq()
1637 dco_freq += ((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * in skl_ddi_wrpll_get_freq()
1795 hw_state->cfgcr1, in skl_dump_hw_state()
2638 p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK; in icl_ddi_combo_pll_get_freq()
2639 p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK; in icl_ddi_combo_pll_get_freq()
2641 if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) in icl_ddi_combo_pll_get_freq()
2642 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >> in icl_ddi_combo_pll_get_freq()
2705 pll_state->cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params->qdiv_ratio) | in icl_calc_dpll_state()
2711 pll_state->cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL; in icl_calc_dpll_state()
2713 pll_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400; in icl_calc_dpll_state()
3465 hw_state->cfgcr1 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR1(id)); in icl_pll_get_hw_state()
3468 hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id)); in icl_pll_get_hw_state()
3472 hw_state->cfgcr1 = intel_de_read(dev_priv, in icl_pll_get_hw_state()
3477 hw_state->cfgcr1 = intel_de_read(dev_priv, in icl_pll_get_hw_state()
3483 hw_state->cfgcr1 = intel_de_read(dev_priv, in icl_pll_get_hw_state()
3488 hw_state->cfgcr1 = intel_de_read(dev_priv, in icl_pll_get_hw_state()
3545 intel_de_write(dev_priv, cfgcr1_reg, hw_state->cfgcr1); in icl_dpll_write()
3884 hw_state->cfgcr0, hw_state->cfgcr1, in icl_dump_hw_state()