Lines Matching refs:nssc
898 refclk = dev_priv->dpll.ref_clks.nssc; in hsw_ddi_wrpll_get_freq()
1059 i915->dpll.ref_clks.nssc = 24000; in hsw_update_dpll_ref_clks()
1061 i915->dpll.ref_clks.nssc = 135000; in hsw_update_dpll_ref_clks()
1552 i915->dpll.ref_clks.nssc, in skl_ddi_hdmi_pll_dividers()
1579 int ref_clock = i915->dpll.ref_clks.nssc; in skl_ddi_wrpll_get_freq()
1786 i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref; in skl_update_dpll_ref_clks()
2231 return chv_calc_dpll_params(i915->dpll.ref_clks.nssc, &clock); in bxt_ddi_pll_get_freq()
2270 i915->dpll.ref_clks.nssc = 100000; in bxt_update_dpll_ref_clks()
2412 i915->dpll.ref_clks.nssc == 38400; in ehl_combo_pll_div_frac_wa_needed()
2506 dev_priv->dpll.ref_clks.nssc == 24000 ? in icl_calc_dp_combo_pll()
2529 switch (dev_priv->dpll.ref_clks.nssc) { in icl_calc_tbt_pll()
2531 MISSING_CASE(dev_priv->dpll.ref_clks.nssc); in icl_calc_tbt_pll()
2542 switch (dev_priv->dpll.ref_clks.nssc) { in icl_calc_tbt_pll()
2544 MISSING_CASE(dev_priv->dpll.ref_clks.nssc); in icl_calc_tbt_pll()
2574 int ref_clock = i915->dpll.ref_clks.nssc; in icl_wrpll_ref_clock()
2800 int refclk_khz = dev_priv->dpll.ref_clks.nssc; in icl_calc_mg_pll_state()
3008 ref_clock = dev_priv->dpll.ref_clks.nssc; in icl_ddi_mg_pll_get_freq()
3353 if (dev_priv->dpll.ref_clks.nssc == 38400) { in mg_pll_get_hw_state()
3871 i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref; in icl_update_dpll_ref_clks()