Lines Matching refs:dev_priv
132 static unsigned int intel_fbc_cfb_size(struct drm_i915_private *dev_priv, in intel_fbc_cfb_size() argument
137 if (DISPLAY_VER(dev_priv) == 7) in intel_fbc_cfb_size()
139 else if (DISPLAY_VER(dev_priv) >= 8) in intel_fbc_cfb_size()
142 return lines * intel_fbc_cfb_stride(dev_priv, cache); in intel_fbc_cfb_size()
145 static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv) in i8xx_fbc_deactivate() argument
150 fbc_ctl = intel_de_read(dev_priv, FBC_CONTROL); in i8xx_fbc_deactivate()
155 intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl); in i8xx_fbc_deactivate()
158 if (intel_de_wait_for_clear(dev_priv, FBC_STATUS, in i8xx_fbc_deactivate()
160 drm_dbg_kms(&dev_priv->drm, "FBC idle timed out\n"); in i8xx_fbc_deactivate()
165 static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) in i8xx_fbc_activate() argument
167 struct intel_fbc *fbc = &dev_priv->fbc; in i8xx_fbc_activate()
176 if (DISPLAY_VER(dev_priv) == 2) in i8xx_fbc_activate()
183 intel_de_write(dev_priv, FBC_TAG(i), 0); in i8xx_fbc_activate()
185 if (DISPLAY_VER(dev_priv) == 4) { in i8xx_fbc_activate()
193 intel_de_write(dev_priv, FBC_CONTROL2, fbc_ctl2); in i8xx_fbc_activate()
194 intel_de_write(dev_priv, FBC_FENCE_OFF, in i8xx_fbc_activate()
201 if (IS_I945GM(dev_priv)) in i8xx_fbc_activate()
206 intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl); in i8xx_fbc_activate()
209 static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv) in i8xx_fbc_is_active() argument
211 return intel_de_read(dev_priv, FBC_CONTROL) & FBC_CTL_EN; in i8xx_fbc_is_active()
229 static void g4x_fbc_activate(struct drm_i915_private *dev_priv) in g4x_fbc_activate() argument
231 struct intel_fbc_reg_params *params = &dev_priv->fbc.params; in g4x_fbc_activate()
236 dpfc_ctl |= g4x_dpfc_ctl_limit(dev_priv); in g4x_fbc_activate()
240 intel_de_write(dev_priv, DPFC_FENCE_YOFF, in g4x_fbc_activate()
243 intel_de_write(dev_priv, DPFC_FENCE_YOFF, 0); in g4x_fbc_activate()
247 intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); in g4x_fbc_activate()
250 static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv) in g4x_fbc_deactivate() argument
255 dpfc_ctl = intel_de_read(dev_priv, DPFC_CONTROL); in g4x_fbc_deactivate()
258 intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl); in g4x_fbc_deactivate()
262 static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv) in g4x_fbc_is_active() argument
264 return intel_de_read(dev_priv, DPFC_CONTROL) & DPFC_CTL_EN; in g4x_fbc_is_active()
267 static void i8xx_fbc_recompress(struct drm_i915_private *dev_priv) in i8xx_fbc_recompress() argument
269 struct intel_fbc_reg_params *params = &dev_priv->fbc.params; in i8xx_fbc_recompress()
272 spin_lock_irq(&dev_priv->uncore.lock); in i8xx_fbc_recompress()
273 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), in i8xx_fbc_recompress()
274 intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane))); in i8xx_fbc_recompress()
275 spin_unlock_irq(&dev_priv->uncore.lock); in i8xx_fbc_recompress()
278 static void i965_fbc_recompress(struct drm_i915_private *dev_priv) in i965_fbc_recompress() argument
280 struct intel_fbc_reg_params *params = &dev_priv->fbc.params; in i965_fbc_recompress()
283 spin_lock_irq(&dev_priv->uncore.lock); in i965_fbc_recompress()
284 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), in i965_fbc_recompress()
285 intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane))); in i965_fbc_recompress()
286 spin_unlock_irq(&dev_priv->uncore.lock); in i965_fbc_recompress()
290 static void snb_fbc_recompress(struct drm_i915_private *dev_priv) in snb_fbc_recompress() argument
292 intel_de_write(dev_priv, MSG_FBC_REND_STATE, FBC_REND_NUKE); in snb_fbc_recompress()
293 intel_de_posting_read(dev_priv, MSG_FBC_REND_STATE); in snb_fbc_recompress()
296 static void intel_fbc_recompress(struct drm_i915_private *dev_priv) in intel_fbc_recompress() argument
298 struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_recompress()
302 if (DISPLAY_VER(dev_priv) >= 6) in intel_fbc_recompress()
303 snb_fbc_recompress(dev_priv); in intel_fbc_recompress()
304 else if (DISPLAY_VER(dev_priv) >= 4) in intel_fbc_recompress()
305 i965_fbc_recompress(dev_priv); in intel_fbc_recompress()
307 i8xx_fbc_recompress(dev_priv); in intel_fbc_recompress()
310 static void ilk_fbc_activate(struct drm_i915_private *dev_priv) in ilk_fbc_activate() argument
312 struct intel_fbc_reg_params *params = &dev_priv->fbc.params; in ilk_fbc_activate()
317 dpfc_ctl |= g4x_dpfc_ctl_limit(dev_priv); in ilk_fbc_activate()
321 if (IS_IRONLAKE(dev_priv)) in ilk_fbc_activate()
323 if (IS_SANDYBRIDGE(dev_priv)) { in ilk_fbc_activate()
324 intel_de_write(dev_priv, SNB_DPFC_CTL_SA, in ilk_fbc_activate()
326 intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, in ilk_fbc_activate()
330 if (IS_SANDYBRIDGE(dev_priv)) { in ilk_fbc_activate()
331 intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0); in ilk_fbc_activate()
332 intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0); in ilk_fbc_activate()
336 intel_de_write(dev_priv, ILK_DPFC_FENCE_YOFF, in ilk_fbc_activate()
339 intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); in ilk_fbc_activate()
342 static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv) in ilk_fbc_deactivate() argument
347 dpfc_ctl = intel_de_read(dev_priv, ILK_DPFC_CONTROL); in ilk_fbc_deactivate()
350 intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl); in ilk_fbc_deactivate()
354 static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv) in ilk_fbc_is_active() argument
356 return intel_de_read(dev_priv, ILK_DPFC_CONTROL) & DPFC_CTL_EN; in ilk_fbc_is_active()
359 static void gen7_fbc_activate(struct drm_i915_private *dev_priv) in gen7_fbc_activate() argument
361 struct intel_fbc *fbc = &dev_priv->fbc; in gen7_fbc_activate()
365 if (DISPLAY_VER(dev_priv) >= 10) { in gen7_fbc_activate()
372 intel_de_write(dev_priv, GLK_FBC_STRIDE, val); in gen7_fbc_activate()
373 } else if (DISPLAY_VER(dev_priv) == 9) { in gen7_fbc_activate()
381 intel_de_rmw(dev_priv, CHICKEN_MISC_4, in gen7_fbc_activate()
387 if (IS_IVYBRIDGE(dev_priv)) in gen7_fbc_activate()
390 dpfc_ctl |= g4x_dpfc_ctl_limit(dev_priv); in gen7_fbc_activate()
394 intel_de_write(dev_priv, SNB_DPFC_CTL_SA, in gen7_fbc_activate()
396 intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, in gen7_fbc_activate()
398 } else if (dev_priv->ggtt.num_fences) { in gen7_fbc_activate()
399 intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0); in gen7_fbc_activate()
400 intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0); in gen7_fbc_activate()
403 if (dev_priv->fbc.false_color) in gen7_fbc_activate()
406 intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); in gen7_fbc_activate()
409 static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv) in intel_fbc_hw_is_active() argument
411 if (DISPLAY_VER(dev_priv) >= 5) in intel_fbc_hw_is_active()
412 return ilk_fbc_is_active(dev_priv); in intel_fbc_hw_is_active()
413 else if (IS_GM45(dev_priv)) in intel_fbc_hw_is_active()
414 return g4x_fbc_is_active(dev_priv); in intel_fbc_hw_is_active()
416 return i8xx_fbc_is_active(dev_priv); in intel_fbc_hw_is_active()
419 static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv) in intel_fbc_hw_activate() argument
421 struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_hw_activate()
428 if (DISPLAY_VER(dev_priv) >= 7) in intel_fbc_hw_activate()
429 gen7_fbc_activate(dev_priv); in intel_fbc_hw_activate()
430 else if (DISPLAY_VER(dev_priv) >= 5) in intel_fbc_hw_activate()
431 ilk_fbc_activate(dev_priv); in intel_fbc_hw_activate()
432 else if (IS_GM45(dev_priv)) in intel_fbc_hw_activate()
433 g4x_fbc_activate(dev_priv); in intel_fbc_hw_activate()
435 i8xx_fbc_activate(dev_priv); in intel_fbc_hw_activate()
438 static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv) in intel_fbc_hw_deactivate() argument
440 struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_hw_deactivate()
446 if (DISPLAY_VER(dev_priv) >= 5) in intel_fbc_hw_deactivate()
447 ilk_fbc_deactivate(dev_priv); in intel_fbc_hw_deactivate()
448 else if (IS_GM45(dev_priv)) in intel_fbc_hw_deactivate()
449 g4x_fbc_deactivate(dev_priv); in intel_fbc_hw_deactivate()
451 i8xx_fbc_deactivate(dev_priv); in intel_fbc_hw_deactivate()
463 bool intel_fbc_is_active(struct drm_i915_private *dev_priv) in intel_fbc_is_active() argument
465 return dev_priv->fbc.active; in intel_fbc_is_active()
468 static void intel_fbc_activate(struct drm_i915_private *dev_priv) in intel_fbc_activate() argument
470 intel_fbc_hw_activate(dev_priv); in intel_fbc_activate()
471 intel_fbc_recompress(dev_priv); in intel_fbc_activate()
474 static void intel_fbc_deactivate(struct drm_i915_private *dev_priv, in intel_fbc_deactivate() argument
477 struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_deactivate()
479 drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock)); in intel_fbc_deactivate()
482 intel_fbc_hw_deactivate(dev_priv); in intel_fbc_deactivate()
495 static u64 intel_fbc_stolen_end(struct drm_i915_private *dev_priv) in intel_fbc_stolen_end() argument
503 if (IS_BROADWELL(dev_priv) || (DISPLAY_VER(dev_priv) == 9 && in intel_fbc_stolen_end()
504 !IS_BROXTON(dev_priv))) in intel_fbc_stolen_end()
505 end = resource_size(&dev_priv->dsm) - 8 * 1024 * 1024; in intel_fbc_stolen_end()
509 return min(end, intel_fbc_cfb_base_max(dev_priv)); in intel_fbc_stolen_end()
517 static int intel_fbc_max_limit(struct drm_i915_private *dev_priv) in intel_fbc_max_limit() argument
520 if (IS_G4X(dev_priv)) in intel_fbc_max_limit()
530 static int find_compression_limit(struct drm_i915_private *dev_priv, in find_compression_limit() argument
533 struct intel_fbc *fbc = &dev_priv->fbc; in find_compression_limit()
534 u64 end = intel_fbc_stolen_end(dev_priv); in find_compression_limit()
540 ret = i915_gem_stolen_insert_node_in_range(dev_priv, &fbc->compressed_fb, in find_compression_limit()
545 for (; limit <= intel_fbc_max_limit(dev_priv); limit <<= 1) { in find_compression_limit()
546 ret = i915_gem_stolen_insert_node_in_range(dev_priv, &fbc->compressed_fb, in find_compression_limit()
555 static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv, in intel_fbc_alloc_cfb() argument
558 struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_alloc_cfb()
561 drm_WARN_ON(&dev_priv->drm, in intel_fbc_alloc_cfb()
563 drm_WARN_ON(&dev_priv->drm, in intel_fbc_alloc_cfb()
566 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) { in intel_fbc_alloc_cfb()
567 ret = i915_gem_stolen_insert_node(dev_priv, &fbc->compressed_llb, in intel_fbc_alloc_cfb()
573 ret = find_compression_limit(dev_priv, size, min_limit); in intel_fbc_alloc_cfb()
577 drm_info_once(&dev_priv->drm, in intel_fbc_alloc_cfb()
582 drm_dbg_kms(&dev_priv->drm, in intel_fbc_alloc_cfb()
590 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_llb); in intel_fbc_alloc_cfb()
592 if (drm_mm_initialized(&dev_priv->mm.stolen)) in intel_fbc_alloc_cfb()
593 …drm_info_once(&dev_priv->drm, "not enough stolen space for compressed buffer (need %d more bytes),… in intel_fbc_alloc_cfb()
597 static void intel_fbc_program_cfb(struct drm_i915_private *dev_priv) in intel_fbc_program_cfb() argument
599 struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_program_cfb()
601 if (DISPLAY_VER(dev_priv) >= 5) { in intel_fbc_program_cfb()
602 intel_de_write(dev_priv, ILK_DPFC_CB_BASE, in intel_fbc_program_cfb()
604 } else if (IS_GM45(dev_priv)) { in intel_fbc_program_cfb()
605 intel_de_write(dev_priv, DPFC_CB_BASE, in intel_fbc_program_cfb()
608 GEM_BUG_ON(range_overflows_end_t(u64, dev_priv->dsm.start, in intel_fbc_program_cfb()
611 GEM_BUG_ON(range_overflows_end_t(u64, dev_priv->dsm.start, in intel_fbc_program_cfb()
615 intel_de_write(dev_priv, FBC_CFB_BASE, in intel_fbc_program_cfb()
616 dev_priv->dsm.start + fbc->compressed_fb.start); in intel_fbc_program_cfb()
617 intel_de_write(dev_priv, FBC_LL_BASE, in intel_fbc_program_cfb()
618 dev_priv->dsm.start + fbc->compressed_llb.start); in intel_fbc_program_cfb()
622 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) in __intel_fbc_cleanup_cfb() argument
624 struct intel_fbc *fbc = &dev_priv->fbc; in __intel_fbc_cleanup_cfb()
626 if (WARN_ON(intel_fbc_hw_is_active(dev_priv))) in __intel_fbc_cleanup_cfb()
630 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_llb); in __intel_fbc_cleanup_cfb()
632 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb); in __intel_fbc_cleanup_cfb()
635 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) in intel_fbc_cleanup_cfb() argument
637 struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_cleanup_cfb()
639 if (!HAS_FBC(dev_priv)) in intel_fbc_cleanup_cfb()
643 __intel_fbc_cleanup_cfb(dev_priv); in intel_fbc_cleanup_cfb()
647 static bool stride_is_valid(struct drm_i915_private *dev_priv, in stride_is_valid() argument
651 if (drm_WARN_ON_ONCE(&dev_priv->drm, (stride & (64 - 1)) != 0)) in stride_is_valid()
658 if (DISPLAY_VER(dev_priv) == 2 || DISPLAY_VER(dev_priv) == 3) in stride_is_valid()
661 if (DISPLAY_VER(dev_priv) == 4 && !IS_G4X(dev_priv) && stride < 2048) in stride_is_valid()
665 if ((DISPLAY_VER(dev_priv) == 9 || IS_GEMINILAKE(dev_priv)) && in stride_is_valid()
675 static bool pixel_format_is_valid(struct drm_i915_private *dev_priv, in pixel_format_is_valid() argument
685 if (DISPLAY_VER(dev_priv) == 2) in pixel_format_is_valid()
688 if (IS_G4X(dev_priv)) in pixel_format_is_valid()
696 static bool rotation_is_valid(struct drm_i915_private *dev_priv, in rotation_is_valid() argument
699 if (DISPLAY_VER(dev_priv) >= 9 && pixel_format == DRM_FORMAT_RGB565 && in rotation_is_valid()
702 else if (DISPLAY_VER(dev_priv) <= 4 && !IS_G4X(dev_priv) && in rotation_is_valid()
717 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_fbc_hw_tracking_covers_screen() local
718 struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_hw_tracking_covers_screen()
721 if (DISPLAY_VER(dev_priv) >= 10) { in intel_fbc_hw_tracking_covers_screen()
724 } else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) { in intel_fbc_hw_tracking_covers_screen()
727 } else if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) { in intel_fbc_hw_tracking_covers_screen()
743 static bool tiling_is_valid(struct drm_i915_private *dev_priv, in tiling_is_valid() argument
750 return DISPLAY_VER(dev_priv) >= 9; in tiling_is_valid()
762 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_fbc_update_state_cache() local
763 struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_update_state_cache()
772 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) in intel_fbc_update_state_cache()
797 drm_WARN_ON(&dev_priv->drm, plane_state->flags & PLANE_HAS_FENCE && in intel_fbc_update_state_cache()
809 static bool intel_fbc_cfb_size_changed(struct drm_i915_private *dev_priv) in intel_fbc_cfb_size_changed() argument
811 struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_cfb_size_changed()
813 return intel_fbc_cfb_size(dev_priv, &fbc->state_cache) > in intel_fbc_cfb_size_changed()
817 static u16 intel_fbc_override_cfb_stride(struct drm_i915_private *dev_priv, in intel_fbc_override_cfb_stride() argument
821 unsigned int stride_aligned = intel_fbc_cfb_stride(dev_priv, cache); in intel_fbc_override_cfb_stride()
831 (DISPLAY_VER(dev_priv) == 9 && in intel_fbc_override_cfb_stride()
838 static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv) in intel_fbc_can_enable() argument
840 struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_can_enable()
842 if (intel_vgpu_active(dev_priv)) { in intel_fbc_can_enable()
847 if (!dev_priv->params.enable_fbc) { in intel_fbc_can_enable()
862 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_fbc_can_activate() local
863 struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_can_activate()
866 if (!intel_fbc_can_enable(dev_priv)) in intel_fbc_can_activate()
909 if (DISPLAY_VER(dev_priv) < 9 && cache->fence_id < 0) { in intel_fbc_can_activate()
914 if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) { in intel_fbc_can_activate()
919 if (!rotation_is_valid(dev_priv, cache->fb.format->format, in intel_fbc_can_activate()
925 if (!tiling_is_valid(dev_priv, cache->fb.modifier)) { in intel_fbc_can_activate()
930 if (!stride_is_valid(dev_priv, cache->fb.modifier, in intel_fbc_can_activate()
943 if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && in intel_fbc_can_activate()
944 cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) { in intel_fbc_can_activate()
959 if (intel_fbc_cfb_size_changed(dev_priv)) { in intel_fbc_can_activate()
969 if (DISPLAY_VER(dev_priv) >= 9 && in intel_fbc_can_activate()
976 if (DISPLAY_VER(dev_priv) >= 11 && in intel_fbc_can_activate()
987 if (fbc->state_cache.psr2_active && DISPLAY_VER(dev_priv) >= 12) { in intel_fbc_can_activate()
998 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_fbc_get_reg_params() local
999 struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_get_reg_params()
1019 params->cfb_stride = intel_fbc_cfb_stride(dev_priv, cache); in intel_fbc_get_reg_params()
1020 params->cfb_size = intel_fbc_cfb_size(dev_priv, cache); in intel_fbc_get_reg_params()
1021 params->override_cfb_stride = intel_fbc_override_cfb_stride(dev_priv, cache); in intel_fbc_get_reg_params()
1029 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_fbc_can_flip_nuke() local
1030 const struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_can_flip_nuke()
1052 if (params->cfb_stride != intel_fbc_cfb_stride(dev_priv, cache)) in intel_fbc_can_flip_nuke()
1055 if (params->cfb_size != intel_fbc_cfb_size(dev_priv, cache)) in intel_fbc_can_flip_nuke()
1058 if (params->override_cfb_stride != intel_fbc_override_cfb_stride(dev_priv, cache)) in intel_fbc_can_flip_nuke()
1072 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_fbc_pre_update() local
1073 struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_pre_update()
1089 intel_fbc_deactivate(dev_priv, reason); in intel_fbc_pre_update()
1105 DISPLAY_VER(dev_priv) >= 10) in intel_fbc_pre_update()
1122 static void __intel_fbc_disable(struct drm_i915_private *dev_priv) in __intel_fbc_disable() argument
1124 struct intel_fbc *fbc = &dev_priv->fbc; in __intel_fbc_disable()
1127 drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock)); in __intel_fbc_disable()
1128 drm_WARN_ON(&dev_priv->drm, !fbc->crtc); in __intel_fbc_disable()
1129 drm_WARN_ON(&dev_priv->drm, fbc->active); in __intel_fbc_disable()
1131 drm_dbg_kms(&dev_priv->drm, "Disabling FBC on pipe %c\n", in __intel_fbc_disable()
1134 __intel_fbc_cleanup_cfb(dev_priv); in __intel_fbc_disable()
1141 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in __intel_fbc_post_update() local
1142 struct intel_fbc *fbc = &dev_priv->fbc; in __intel_fbc_post_update()
1144 drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock)); in __intel_fbc_post_update()
1151 if (!dev_priv->params.enable_fbc) { in __intel_fbc_post_update()
1152 intel_fbc_deactivate(dev_priv, "disabled at runtime per module param"); in __intel_fbc_post_update()
1153 __intel_fbc_disable(dev_priv); in __intel_fbc_post_update()
1164 intel_fbc_activate(dev_priv); in __intel_fbc_post_update()
1166 intel_fbc_deactivate(dev_priv, "frontbuffer write"); in __intel_fbc_post_update()
1172 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_fbc_post_update() local
1176 struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_post_update()
1194 void intel_fbc_invalidate(struct drm_i915_private *dev_priv, in intel_fbc_invalidate() argument
1198 struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_invalidate()
1200 if (!HAS_FBC(dev_priv)) in intel_fbc_invalidate()
1211 intel_fbc_deactivate(dev_priv, "frontbuffer write"); in intel_fbc_invalidate()
1216 void intel_fbc_flush(struct drm_i915_private *dev_priv, in intel_fbc_flush() argument
1219 struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_flush()
1221 if (!HAS_FBC(dev_priv)) in intel_fbc_flush()
1234 intel_fbc_recompress(dev_priv); in intel_fbc_flush()
1255 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, in intel_fbc_choose_crtc() argument
1258 struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_choose_crtc()
1271 if (!intel_fbc_can_enable(dev_priv)) in intel_fbc_choose_crtc()
1315 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_fbc_enable() local
1321 struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_enable()
1338 !intel_fbc_cfb_size_changed(dev_priv)) in intel_fbc_enable()
1341 __intel_fbc_disable(dev_priv); in intel_fbc_enable()
1344 drm_WARN_ON(&dev_priv->drm, fbc->active); in intel_fbc_enable()
1352 if (intel_fbc_alloc_cfb(dev_priv, in intel_fbc_enable()
1353 intel_fbc_cfb_size(dev_priv, cache), min_limit)) { in intel_fbc_enable()
1359 drm_dbg_kms(&dev_priv->drm, "Enabling FBC on pipe %c\n", in intel_fbc_enable()
1365 intel_fbc_program_cfb(dev_priv); in intel_fbc_enable()
1378 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_fbc_disable() local
1380 struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_disable()
1387 __intel_fbc_disable(dev_priv); in intel_fbc_disable()
1419 void intel_fbc_global_disable(struct drm_i915_private *dev_priv) in intel_fbc_global_disable() argument
1421 struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_global_disable()
1423 if (!HAS_FBC(dev_priv)) in intel_fbc_global_disable()
1428 drm_WARN_ON(&dev_priv->drm, fbc->crtc->active); in intel_fbc_global_disable()
1429 __intel_fbc_disable(dev_priv); in intel_fbc_global_disable()
1436 struct drm_i915_private *dev_priv = in intel_fbc_underrun_work_fn() local
1438 struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_underrun_work_fn()
1446 drm_dbg_kms(&dev_priv->drm, "Disabling FBC due to FIFO underrun.\n"); in intel_fbc_underrun_work_fn()
1449 intel_fbc_deactivate(dev_priv, "FIFO underrun"); in intel_fbc_underrun_work_fn()
1461 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv) in intel_fbc_reset_underrun() argument
1465 cancel_work_sync(&dev_priv->fbc.underrun_work); in intel_fbc_reset_underrun()
1467 ret = mutex_lock_interruptible(&dev_priv->fbc.lock); in intel_fbc_reset_underrun()
1471 if (dev_priv->fbc.underrun_detected) { in intel_fbc_reset_underrun()
1472 drm_dbg_kms(&dev_priv->drm, in intel_fbc_reset_underrun()
1474 dev_priv->fbc.no_fbc_reason = "FIFO underrun cleared"; in intel_fbc_reset_underrun()
1477 dev_priv->fbc.underrun_detected = false; in intel_fbc_reset_underrun()
1478 mutex_unlock(&dev_priv->fbc.lock); in intel_fbc_reset_underrun()
1497 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv) in intel_fbc_handle_fifo_underrun_irq() argument
1499 struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_handle_fifo_underrun_irq()
1501 if (!HAS_FBC(dev_priv)) in intel_fbc_handle_fifo_underrun_irq()
1525 static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv) in intel_sanitize_fbc_option() argument
1527 if (dev_priv->params.enable_fbc >= 0) in intel_sanitize_fbc_option()
1528 return !!dev_priv->params.enable_fbc; in intel_sanitize_fbc_option()
1530 if (!HAS_FBC(dev_priv)) in intel_sanitize_fbc_option()
1533 if (IS_BROADWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 9) in intel_sanitize_fbc_option()
1539 static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv) in need_fbc_vtd_wa() argument
1543 (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) { in need_fbc_vtd_wa()
1544 drm_info(&dev_priv->drm, in need_fbc_vtd_wa()
1558 void intel_fbc_init(struct drm_i915_private *dev_priv) in intel_fbc_init() argument
1560 struct intel_fbc *fbc = &dev_priv->fbc; in intel_fbc_init()
1566 if (!drm_mm_initialized(&dev_priv->mm.stolen)) in intel_fbc_init()
1567 mkwrite_device_info(dev_priv)->display.has_fbc = false; in intel_fbc_init()
1569 if (need_fbc_vtd_wa(dev_priv)) in intel_fbc_init()
1570 mkwrite_device_info(dev_priv)->display.has_fbc = false; in intel_fbc_init()
1572 dev_priv->params.enable_fbc = intel_sanitize_fbc_option(dev_priv); in intel_fbc_init()
1573 drm_dbg_kms(&dev_priv->drm, "Sanitized enable_fbc value: %d\n", in intel_fbc_init()
1574 dev_priv->params.enable_fbc); in intel_fbc_init()
1576 if (!HAS_FBC(dev_priv)) { in intel_fbc_init()
1584 if (intel_fbc_hw_is_active(dev_priv)) in intel_fbc_init()
1585 intel_fbc_hw_deactivate(dev_priv); in intel_fbc_init()