Lines Matching refs:dev_priv
102 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, in get_gmbus_pin() argument
105 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) in get_gmbus_pin()
107 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) in get_gmbus_pin()
109 else if (HAS_PCH_CNP(dev_priv)) in get_gmbus_pin()
111 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in get_gmbus_pin()
113 else if (DISPLAY_VER(dev_priv) == 9) in get_gmbus_pin()
115 else if (IS_BROADWELL(dev_priv)) in get_gmbus_pin()
121 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, in intel_gmbus_is_valid_pin() argument
126 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) in intel_gmbus_is_valid_pin()
128 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) in intel_gmbus_is_valid_pin()
130 else if (HAS_PCH_CNP(dev_priv)) in intel_gmbus_is_valid_pin()
132 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in intel_gmbus_is_valid_pin()
134 else if (DISPLAY_VER(dev_priv) == 9) in intel_gmbus_is_valid_pin()
136 else if (IS_BROADWELL(dev_priv)) in intel_gmbus_is_valid_pin()
141 return pin < size && get_gmbus_pin(dev_priv, pin)->name; in intel_gmbus_is_valid_pin()
155 intel_gmbus_reset(struct drm_i915_private *dev_priv) in intel_gmbus_reset() argument
157 intel_de_write(dev_priv, GMBUS0, 0); in intel_gmbus_reset()
158 intel_de_write(dev_priv, GMBUS4, 0); in intel_gmbus_reset()
161 static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv, in pnv_gmbus_clock_gating() argument
167 val = intel_de_read(dev_priv, DSPCLK_GATE_D); in pnv_gmbus_clock_gating()
172 intel_de_write(dev_priv, DSPCLK_GATE_D, val); in pnv_gmbus_clock_gating()
175 static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv, in pch_gmbus_clock_gating() argument
180 val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D); in pch_gmbus_clock_gating()
185 intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val); in pch_gmbus_clock_gating()
188 static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv, in bxt_gmbus_clock_gating() argument
193 val = intel_de_read(dev_priv, GEN9_CLKGATE_DIS_4); in bxt_gmbus_clock_gating()
198 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_4, val); in bxt_gmbus_clock_gating()
203 struct drm_i915_private *i915 = bus->dev_priv; in get_reserved()
219 struct intel_uncore *uncore = &bus->dev_priv->uncore; in get_clock()
234 struct intel_uncore *uncore = &bus->dev_priv->uncore; in get_data()
249 struct intel_uncore *uncore = &bus->dev_priv->uncore; in set_clock()
268 struct intel_uncore *uncore = &bus->dev_priv->uncore; in set_data()
288 struct drm_i915_private *dev_priv = bus->dev_priv; in intel_gpio_pre_xfer() local
290 intel_gmbus_reset(dev_priv); in intel_gpio_pre_xfer()
292 if (IS_PINEVIEW(dev_priv)) in intel_gpio_pre_xfer()
293 pnv_gmbus_clock_gating(dev_priv, false); in intel_gpio_pre_xfer()
307 struct drm_i915_private *dev_priv = bus->dev_priv; in intel_gpio_post_xfer() local
312 if (IS_PINEVIEW(dev_priv)) in intel_gpio_post_xfer()
313 pnv_gmbus_clock_gating(dev_priv, true); in intel_gpio_post_xfer()
319 struct drm_i915_private *dev_priv = bus->dev_priv; in intel_gpio_setup() local
324 bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio); in intel_gpio_setup()
337 static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en) in gmbus_wait() argument
347 if (!HAS_GMBUS_IRQ(dev_priv)) in gmbus_wait()
350 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); in gmbus_wait()
351 intel_de_write_fw(dev_priv, GMBUS4, irq_en); in gmbus_wait()
354 ret = wait_for_us((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status, in gmbus_wait()
357 ret = wait_for((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status, in gmbus_wait()
360 intel_de_write_fw(dev_priv, GMBUS4, 0); in gmbus_wait()
361 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); in gmbus_wait()
370 gmbus_wait_idle(struct drm_i915_private *dev_priv) in gmbus_wait_idle() argument
378 if (HAS_GMBUS_IRQ(dev_priv)) in gmbus_wait_idle()
381 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); in gmbus_wait_idle()
382 intel_de_write_fw(dev_priv, GMBUS4, irq_enable); in gmbus_wait_idle()
384 ret = intel_wait_for_register_fw(&dev_priv->uncore, in gmbus_wait_idle()
388 intel_de_write_fw(dev_priv, GMBUS4, 0); in gmbus_wait_idle()
389 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); in gmbus_wait_idle()
394 static unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv) in gmbus_max_xfer_size() argument
396 return DISPLAY_VER(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : in gmbus_max_xfer_size()
401 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, in gmbus_xfer_read_chunk() argument
406 bool burst_read = len > gmbus_max_xfer_size(dev_priv); in gmbus_xfer_read_chunk()
419 intel_de_write_fw(dev_priv, GMBUS0, in gmbus_xfer_read_chunk()
423 intel_de_write_fw(dev_priv, GMBUS1, in gmbus_xfer_read_chunk()
429 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); in gmbus_xfer_read_chunk()
433 val = intel_de_read_fw(dev_priv, GMBUS3); in gmbus_xfer_read_chunk()
444 intel_de_write_fw(dev_priv, GMBUS0, gmbus0_reg); in gmbus_xfer_read_chunk()
461 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, in gmbus_xfer_read() argument
470 if (HAS_GMBUS_BURST_READ(dev_priv)) in gmbus_xfer_read()
473 len = min(rx_size, gmbus_max_xfer_size(dev_priv)); in gmbus_xfer_read()
475 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len, in gmbus_xfer_read()
488 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, in gmbus_xfer_write_chunk() argument
501 intel_de_write_fw(dev_priv, GMBUS3, val); in gmbus_xfer_write_chunk()
502 intel_de_write_fw(dev_priv, GMBUS1, in gmbus_xfer_write_chunk()
512 intel_de_write_fw(dev_priv, GMBUS3, val); in gmbus_xfer_write_chunk()
514 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); in gmbus_xfer_write_chunk()
523 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg, in gmbus_xfer_write() argument
532 len = min(tx_size, gmbus_max_xfer_size(dev_priv)); in gmbus_xfer_write()
534 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len, in gmbus_xfer_write()
561 gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs, in gmbus_index_xfer() argument
577 intel_de_write_fw(dev_priv, GMBUS5, gmbus5); in gmbus_index_xfer()
580 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg, in gmbus_index_xfer()
583 ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index); in gmbus_index_xfer()
587 intel_de_write_fw(dev_priv, GMBUS5, 0); in gmbus_index_xfer()
599 struct drm_i915_private *dev_priv = bus->dev_priv; in do_gmbus_xfer() local
604 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in do_gmbus_xfer()
605 bxt_gmbus_clock_gating(dev_priv, false); in do_gmbus_xfer()
606 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv)) in do_gmbus_xfer()
607 pch_gmbus_clock_gating(dev_priv, false); in do_gmbus_xfer()
610 intel_de_write_fw(dev_priv, GMBUS0, gmbus0_source | bus->reg0); in do_gmbus_xfer()
615 ret = gmbus_index_xfer(dev_priv, &msgs[i], in do_gmbus_xfer()
619 ret = gmbus_xfer_read(dev_priv, &msgs[i], in do_gmbus_xfer()
622 ret = gmbus_xfer_write(dev_priv, &msgs[i], 0); in do_gmbus_xfer()
626 ret = gmbus_wait(dev_priv, in do_gmbus_xfer()
638 intel_de_write_fw(dev_priv, GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); in do_gmbus_xfer()
644 if (gmbus_wait_idle(dev_priv)) { in do_gmbus_xfer()
645 drm_dbg_kms(&dev_priv->drm, in do_gmbus_xfer()
650 intel_de_write_fw(dev_priv, GMBUS0, 0); in do_gmbus_xfer()
669 if (gmbus_wait_idle(dev_priv)) { in do_gmbus_xfer()
670 drm_dbg_kms(&dev_priv->drm, in do_gmbus_xfer()
680 intel_de_write_fw(dev_priv, GMBUS1, GMBUS_SW_CLR_INT); in do_gmbus_xfer()
681 intel_de_write_fw(dev_priv, GMBUS1, 0); in do_gmbus_xfer()
682 intel_de_write_fw(dev_priv, GMBUS0, 0); in do_gmbus_xfer()
684 drm_dbg_kms(&dev_priv->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n", in do_gmbus_xfer()
695 drm_dbg_kms(&dev_priv->drm, in do_gmbus_xfer()
704 drm_dbg_kms(&dev_priv->drm, in do_gmbus_xfer()
707 intel_de_write_fw(dev_priv, GMBUS0, 0); in do_gmbus_xfer()
717 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in do_gmbus_xfer()
718 bxt_gmbus_clock_gating(dev_priv, true); in do_gmbus_xfer()
719 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv)) in do_gmbus_xfer()
720 pch_gmbus_clock_gating(dev_priv, true); in do_gmbus_xfer()
730 struct drm_i915_private *dev_priv = bus->dev_priv; in gmbus_xfer() local
734 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); in gmbus_xfer()
746 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); in gmbus_xfer()
755 struct drm_i915_private *dev_priv = bus->dev_priv; in intel_gmbus_output_aksv() local
775 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); in intel_gmbus_output_aksv()
776 mutex_lock(&dev_priv->gmbus_mutex); in intel_gmbus_output_aksv()
785 mutex_unlock(&dev_priv->gmbus_mutex); in intel_gmbus_output_aksv()
786 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); in intel_gmbus_output_aksv()
809 struct drm_i915_private *dev_priv = bus->dev_priv; in gmbus_lock_bus() local
811 mutex_lock(&dev_priv->gmbus_mutex); in gmbus_lock_bus()
818 struct drm_i915_private *dev_priv = bus->dev_priv; in gmbus_trylock_bus() local
820 return mutex_trylock(&dev_priv->gmbus_mutex); in gmbus_trylock_bus()
827 struct drm_i915_private *dev_priv = bus->dev_priv; in gmbus_unlock_bus() local
829 mutex_unlock(&dev_priv->gmbus_mutex); in gmbus_unlock_bus()
842 int intel_gmbus_setup(struct drm_i915_private *dev_priv) in intel_gmbus_setup() argument
844 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in intel_gmbus_setup()
849 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_gmbus_setup()
850 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; in intel_gmbus_setup()
851 else if (!HAS_GMCH(dev_priv)) in intel_gmbus_setup()
856 dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE; in intel_gmbus_setup()
858 mutex_init(&dev_priv->gmbus_mutex); in intel_gmbus_setup()
859 init_waitqueue_head(&dev_priv->gmbus_wait_queue); in intel_gmbus_setup()
861 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { in intel_gmbus_setup()
862 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) in intel_gmbus_setup()
865 bus = &dev_priv->gmbus[pin]; in intel_gmbus_setup()
872 get_gmbus_pin(dev_priv, pin)->name); in intel_gmbus_setup()
875 bus->dev_priv = dev_priv; in intel_gmbus_setup()
890 if (IS_I830(dev_priv)) in intel_gmbus_setup()
900 intel_gmbus_reset(dev_priv); in intel_gmbus_setup()
906 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) in intel_gmbus_setup()
909 bus = &dev_priv->gmbus[pin]; in intel_gmbus_setup()
915 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, in intel_gmbus_get_adapter() argument
918 if (drm_WARN_ON(&dev_priv->drm, in intel_gmbus_get_adapter()
919 !intel_gmbus_is_valid_pin(dev_priv, pin))) in intel_gmbus_get_adapter()
922 return &dev_priv->gmbus[pin].adapter; in intel_gmbus_get_adapter()
935 struct drm_i915_private *dev_priv = bus->dev_priv; in intel_gmbus_force_bit() local
937 mutex_lock(&dev_priv->gmbus_mutex); in intel_gmbus_force_bit()
940 drm_dbg_kms(&dev_priv->drm, in intel_gmbus_force_bit()
945 mutex_unlock(&dev_priv->gmbus_mutex); in intel_gmbus_force_bit()
955 void intel_gmbus_teardown(struct drm_i915_private *dev_priv) in intel_gmbus_teardown() argument
960 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { in intel_gmbus_teardown()
961 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) in intel_gmbus_teardown()
964 bus = &dev_priv->gmbus[pin]; in intel_gmbus_teardown()