Lines Matching refs:crtc_state
662 struct intel_crtc_state *crtc_state) in dc3co_is_pipe_port_compatible() argument
665 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; in dc3co_is_pipe_port_compatible()
677 struct intel_crtc_state *crtc_state) in tgl_dc3co_exitline_compute_config() argument
679 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; in tgl_dc3co_exitline_compute_config()
694 if (crtc_state->enable_psr2_sel_fetch) in tgl_dc3co_exitline_compute_config()
700 if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state)) in tgl_dc3co_exitline_compute_config()
712 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; in tgl_dc3co_exitline_compute_config()
717 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; in tgl_dc3co_exitline_compute_config()
721 struct intel_crtc_state *crtc_state) in intel_psr2_sel_fetch_config_valid() argument
732 if (crtc_state->uapi.async_flip) { in intel_psr2_sel_fetch_config_valid()
745 return crtc_state->enable_psr2_sel_fetch = true; in intel_psr2_sel_fetch_config_valid()
749 struct intel_crtc_state *crtc_state) in psr2_granularity_check() argument
752 const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; in psr2_granularity_check()
753 const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; in psr2_granularity_check()
764 if (!crtc_state->enable_psr2_sel_fetch) in psr2_granularity_check()
782 crtc_state->su_y_granularity = y_granularity; in psr2_granularity_check()
787 struct intel_crtc_state *crtc_state) in _compute_psr2_sdp_prior_scanline_indication() argument
789 const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode; in _compute_psr2_sdp_prior_scanline_indication()
797 req_ns = (72 / crtc_state->lane_count) * 1000 / (crtc_state->port_clock / 1000); in _compute_psr2_sdp_prior_scanline_indication()
805 crtc_state->req_psr2_sdp_prior_scanline = true; in _compute_psr2_sdp_prior_scanline_indication()
810 struct intel_crtc_state *crtc_state) in intel_psr2_config_valid() argument
813 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; in intel_psr2_config_valid()
814 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; in intel_psr2_config_valid()
838 if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { in intel_psr2_config_valid()
841 transcoder_name(crtc_state->cpu_transcoder)); in intel_psr2_config_valid()
855 if (crtc_state->dsc.compression_enable) { in intel_psr2_config_valid()
861 if (crtc_state->crc_enabled) { in intel_psr2_config_valid()
881 if (crtc_state->pipe_bpp > max_bpp) { in intel_psr2_config_valid()
884 crtc_state->pipe_bpp, max_bpp); in intel_psr2_config_valid()
889 if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && in intel_psr2_config_valid()
898 if (!crtc_state->enable_psr2_sel_fetch && in intel_psr2_config_valid()
904 if (!psr2_granularity_check(intel_dp, crtc_state)) { in intel_psr2_config_valid()
909 if (!crtc_state->enable_psr2_sel_fetch && in intel_psr2_config_valid()
918 if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) { in intel_psr2_config_valid()
925 if (crtc_state->vrr.enable && in intel_psr2_config_valid()
932 tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); in intel_psr2_config_valid()
937 struct intel_crtc_state *crtc_state, in intel_psr_compute_config() argument
942 &crtc_state->hw.adjusted_mode; in intel_psr_compute_config()
949 if (crtc_state->vrr.enable) in intel_psr_compute_config()
988 crtc_state->has_psr = true; in intel_psr_compute_config()
989 crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); in intel_psr_compute_config()
991 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); in intel_psr_compute_config()
992 intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state, in intel_psr_compute_config()
993 &crtc_state->psr_vsc); in intel_psr_compute_config()
1173 const struct intel_crtc_state *crtc_state) in intel_psr_enable_locked() argument
1183 intel_dp->psr.psr2_enabled = crtc_state->has_psr2; in intel_psr_enable_locked()
1185 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; in intel_psr_enable_locked()
1186 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; in intel_psr_enable_locked()
1188 val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); in intel_psr_enable_locked()
1190 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; in intel_psr_enable_locked()
1191 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; in intel_psr_enable_locked()
1193 crtc_state->req_psr2_sdp_prior_scanline; in intel_psr_enable_locked()
1200 intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc); in intel_psr_enable_locked()
1429 const struct intel_crtc_state *crtc_state) in intel_psr2_disable_plane_sel_fetch() argument
1434 if (!crtc_state->enable_psr2_sel_fetch) in intel_psr2_disable_plane_sel_fetch()
1441 const struct intel_crtc_state *crtc_state, in intel_psr2_program_plane_sel_fetch() argument
1451 if (!crtc_state->enable_psr2_sel_fetch) in intel_psr2_program_plane_sel_fetch()
1482 void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state) in intel_psr2_program_trans_man_trk_ctl() argument
1484 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_psr2_program_trans_man_trk_ctl()
1486 if (!crtc_state->enable_psr2_sel_fetch) in intel_psr2_program_trans_man_trk_ctl()
1489 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder), in intel_psr2_program_trans_man_trk_ctl()
1490 crtc_state->psr2_man_track_ctl); in intel_psr2_program_trans_man_trk_ctl()
1493 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, in psr2_man_trk_ctl_calc() argument
1496 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in psr2_man_trk_ctl_calc()
1516 drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4); in psr2_man_trk_ctl_calc()
1523 crtc_state->psr2_man_track_ctl = val; in psr2_man_trk_ctl_calc()
1542 static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state, in intel_psr2_sel_fetch_pipe_alignment() argument
1545 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_psr2_sel_fetch_pipe_alignment()
1546 const u16 y_alignment = crtc_state->su_y_granularity; in intel_psr2_sel_fetch_pipe_alignment()
1552 if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable) in intel_psr2_sel_fetch_pipe_alignment()
1587 static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state) in psr2_sel_fetch_pipe_state_supported() argument
1589 if (crtc_state->scaler_state.scaler_id >= 0) in psr2_sel_fetch_pipe_state_supported()
1598 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); in intel_psr2_sel_fetch_update() local
1605 if (!crtc_state->enable_psr2_sel_fetch) in intel_psr2_sel_fetch_update()
1608 if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) { in intel_psr2_sel_fetch_update()
1625 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) in intel_psr2_sel_fetch_update()
1690 intel_psr2_sel_fetch_pipe_alignment(crtc_state, &pipe_clip); in intel_psr2_sel_fetch_update()
1700 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc || in intel_psr2_sel_fetch_update()
1716 crtc_state->update_planes |= BIT(plane->id); in intel_psr2_sel_fetch_update()
1720 psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update); in intel_psr2_sel_fetch_update()
1725 const struct intel_crtc_state *crtc_state) in _intel_psr_pre_plane_update() argument
1730 crtc_state->uapi.encoder_mask) { in _intel_psr_pre_plane_update()
1743 needs_to_disable |= !crtc_state->has_psr; in _intel_psr_pre_plane_update()
1744 needs_to_disable |= !crtc_state->active_planes; in _intel_psr_pre_plane_update()
1745 needs_to_disable |= crtc_state->has_psr2 != psr->psr2_enabled; in _intel_psr_pre_plane_update()
1757 struct intel_crtc_state *crtc_state; in intel_psr_pre_plane_update() local
1764 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) in intel_psr_pre_plane_update()
1765 _intel_psr_pre_plane_update(state, crtc_state); in intel_psr_pre_plane_update()
1769 const struct intel_crtc_state *crtc_state) in _intel_psr_post_plane_update() argument
1774 if (!crtc_state->has_psr) in _intel_psr_post_plane_update()
1778 crtc_state->uapi.encoder_mask) { in _intel_psr_post_plane_update()
1784 drm_WARN_ON(&dev_priv->drm, psr->enabled && !crtc_state->active_planes); in _intel_psr_post_plane_update()
1787 if (!psr->enabled && crtc_state->active_planes) in _intel_psr_post_plane_update()
1788 intel_psr_enable_locked(intel_dp, crtc_state); in _intel_psr_post_plane_update()
1791 if (crtc_state->crc_enabled && psr->enabled) in _intel_psr_post_plane_update()
1801 struct intel_crtc_state *crtc_state; in intel_psr_post_plane_update() local
1808 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) in intel_psr_post_plane_update()
1809 _intel_psr_post_plane_update(state, crtc_state); in intel_psr_post_plane_update()
1923 struct drm_crtc_state *crtc_state; in intel_psr_fastset_force() local
1937 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); in intel_psr_fastset_force()
1938 if (IS_ERR(crtc_state)) { in intel_psr_fastset_force()
1939 err = PTR_ERR(crtc_state); in intel_psr_fastset_force()
1944 crtc_state->mode_changed = true; in intel_psr_fastset_force()