Lines Matching refs:transcoder
115 enum transcoder trans_shift; in psr_irq_control()
126 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); in psr_irq_control()
128 trans_shift = intel_dp->psr.transcoder; in psr_irq_control()
184 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_irq_handler()
187 enum transcoder trans_shift; in intel_psr_irq_handler()
192 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); in intel_psr_irq_handler()
194 trans_shift = intel_dp->psr.transcoder; in intel_psr_irq_handler()
475 val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) & in hsw_activate_psr1()
477 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), val); in hsw_activate_psr1()
572 tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); in hsw_activate_psr2()
576 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0); in hsw_activate_psr2()
583 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), 0); in hsw_activate_psr2()
585 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); in hsw_activate_psr2()
589 transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans) in transcoder_has_psr2()
613 val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder)); in psr2_program_idle_frames()
616 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); in psr2_program_idle_frames()
1027 val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); in intel_psr_get_config()
1033 val = intel_de_read(dev_priv, EXITLINE(intel_dp->psr.transcoder)); in intel_psr_get_config()
1044 enum transcoder transcoder = intel_dp->psr.transcoder; in intel_psr_activate() local
1046 if (transcoder_has_psr2(dev_priv, transcoder)) in intel_psr_activate()
1048 intel_de_read(dev_priv, EDP_PSR2_CTL(transcoder)) & EDP_PSR2_ENABLE); in intel_psr_activate()
1051 intel_de_read(dev_priv, EDP_PSR_CTL(transcoder)) & EDP_PSR_ENABLE); in intel_psr_activate()
1067 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_enable_source()
1103 intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp->psr.transcoder), in intel_psr_enable_source()
1131 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), in intel_psr_enable_source()
1156 TRANS_PSR_IIR(intel_dp->psr.transcoder)); in psr_interrupt_error_check()
1160 val &= EDP_PSR_ERROR(intel_dp->psr.transcoder); in psr_interrupt_error_check()
1186 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; in intel_psr_enable_locked()
1216 if (transcoder_has_psr2(dev_priv, intel_dp->psr.transcoder)) { in intel_psr_exit()
1218 EDP_PSR2_CTL(intel_dp->psr.transcoder)); in intel_psr_exit()
1223 EDP_PSR_CTL(intel_dp->psr.transcoder)); in intel_psr_exit()
1232 EDP_PSR2_CTL(intel_dp->psr.transcoder)); in intel_psr_exit()
1236 EDP_PSR2_CTL(intel_dp->psr.transcoder), val); in intel_psr_exit()
1239 EDP_PSR_CTL(intel_dp->psr.transcoder)); in intel_psr_exit()
1243 EDP_PSR_CTL(intel_dp->psr.transcoder), val); in intel_psr_exit()
1255 psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder); in intel_psr_wait_exit_locked()
1258 psr_status = EDP_PSR_STATUS(intel_dp->psr.transcoder); in intel_psr_wait_exit_locked()
1295 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), in intel_psr_disable_locked()
1409 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0, in psr_force_hw_tracking_exit()
1831 EDP_PSR_STATUS(intel_dp->psr.transcoder), in psr_wait_for_idle()
1883 reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder); in __psr_wait_for_idle_locked()
1886 reg = EDP_PSR_STATUS(intel_dp->psr.transcoder); in __psr_wait_for_idle_locked()