Lines Matching refs:cs
17 u32 cmd, *cs; in gen2_emit_flush() local
23 cs = intel_ring_begin(rq, 2 + 4 * num_store_dw); in gen2_emit_flush()
24 if (IS_ERR(cs)) in gen2_emit_flush()
25 return PTR_ERR(cs); in gen2_emit_flush()
27 *cs++ = cmd; in gen2_emit_flush()
29 *cs++ = MI_STORE_DWORD_INDEX; in gen2_emit_flush()
30 *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32); in gen2_emit_flush()
31 *cs++ = 0; in gen2_emit_flush()
32 *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; in gen2_emit_flush()
34 *cs++ = cmd; in gen2_emit_flush()
36 intel_ring_advance(rq, cs); in gen2_emit_flush()
43 u32 cmd, *cs; in gen4_emit_flush_rcs() local
85 cs = intel_ring_begin(rq, i); in gen4_emit_flush_rcs()
86 if (IS_ERR(cs)) in gen4_emit_flush_rcs()
87 return PTR_ERR(cs); in gen4_emit_flush_rcs()
89 *cs++ = cmd; in gen4_emit_flush_rcs()
102 *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; in gen4_emit_flush_rcs()
103 *cs++ = intel_gt_scratch_offset(rq->engine->gt, in gen4_emit_flush_rcs()
106 *cs++ = 0; in gen4_emit_flush_rcs()
107 *cs++ = 0; in gen4_emit_flush_rcs()
110 *cs++ = MI_FLUSH; in gen4_emit_flush_rcs()
112 *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; in gen4_emit_flush_rcs()
113 *cs++ = intel_gt_scratch_offset(rq->engine->gt, in gen4_emit_flush_rcs()
116 *cs++ = 0; in gen4_emit_flush_rcs()
117 *cs++ = 0; in gen4_emit_flush_rcs()
120 *cs++ = cmd; in gen4_emit_flush_rcs()
122 intel_ring_advance(rq, cs); in gen4_emit_flush_rcs()
129 u32 *cs; in gen4_emit_flush_vcs() local
131 cs = intel_ring_begin(rq, 2); in gen4_emit_flush_vcs()
132 if (IS_ERR(cs)) in gen4_emit_flush_vcs()
133 return PTR_ERR(cs); in gen4_emit_flush_vcs()
135 *cs++ = MI_FLUSH; in gen4_emit_flush_vcs()
136 *cs++ = MI_NOOP; in gen4_emit_flush_vcs()
137 intel_ring_advance(rq, cs); in gen4_emit_flush_vcs()
142 static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs, in __gen2_emit_breadcrumb() argument
148 *cs++ = MI_FLUSH; in __gen2_emit_breadcrumb()
151 *cs++ = MI_STORE_DWORD_INDEX; in __gen2_emit_breadcrumb()
152 *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32); in __gen2_emit_breadcrumb()
153 *cs++ = rq->fence.seqno; in __gen2_emit_breadcrumb()
157 *cs++ = MI_STORE_DWORD_INDEX; in __gen2_emit_breadcrumb()
158 *cs++ = I915_GEM_HWS_SEQNO_ADDR; in __gen2_emit_breadcrumb()
159 *cs++ = rq->fence.seqno; in __gen2_emit_breadcrumb()
162 *cs++ = MI_USER_INTERRUPT; in __gen2_emit_breadcrumb()
164 rq->tail = intel_ring_offset(rq, cs); in __gen2_emit_breadcrumb()
167 return cs; in __gen2_emit_breadcrumb()
170 u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs) in gen3_emit_breadcrumb() argument
172 return __gen2_emit_breadcrumb(rq, cs, 16, 8); in gen3_emit_breadcrumb()
175 u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs) in gen5_emit_breadcrumb() argument
177 return __gen2_emit_breadcrumb(rq, cs, 8, 8); in gen5_emit_breadcrumb()
188 u32 *cs, cs_offset = in i830_emit_bb_start() local
194 cs = intel_ring_begin(rq, 6); in i830_emit_bb_start()
195 if (IS_ERR(cs)) in i830_emit_bb_start()
196 return PTR_ERR(cs); in i830_emit_bb_start()
199 *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA; in i830_emit_bb_start()
200 *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096; in i830_emit_bb_start()
201 *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */ in i830_emit_bb_start()
202 *cs++ = cs_offset; in i830_emit_bb_start()
203 *cs++ = 0xdeadbeef; in i830_emit_bb_start()
204 *cs++ = MI_NOOP; in i830_emit_bb_start()
205 intel_ring_advance(rq, cs); in i830_emit_bb_start()
211 cs = intel_ring_begin(rq, 6 + 2); in i830_emit_bb_start()
212 if (IS_ERR(cs)) in i830_emit_bb_start()
213 return PTR_ERR(cs); in i830_emit_bb_start()
220 *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (6 - 2); in i830_emit_bb_start()
221 *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096; in i830_emit_bb_start()
222 *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096; in i830_emit_bb_start()
223 *cs++ = cs_offset; in i830_emit_bb_start()
224 *cs++ = 4096; in i830_emit_bb_start()
225 *cs++ = offset; in i830_emit_bb_start()
227 *cs++ = MI_FLUSH; in i830_emit_bb_start()
228 *cs++ = MI_NOOP; in i830_emit_bb_start()
229 intel_ring_advance(rq, cs); in i830_emit_bb_start()
238 cs = intel_ring_begin(rq, 2); in i830_emit_bb_start()
239 if (IS_ERR(cs)) in i830_emit_bb_start()
240 return PTR_ERR(cs); in i830_emit_bb_start()
242 *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; in i830_emit_bb_start()
243 *cs++ = offset; in i830_emit_bb_start()
244 intel_ring_advance(rq, cs); in i830_emit_bb_start()
253 u32 *cs; in gen3_emit_bb_start() local
258 cs = intel_ring_begin(rq, 2); in gen3_emit_bb_start()
259 if (IS_ERR(cs)) in gen3_emit_bb_start()
260 return PTR_ERR(cs); in gen3_emit_bb_start()
262 *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; in gen3_emit_bb_start()
263 *cs++ = offset; in gen3_emit_bb_start()
264 intel_ring_advance(rq, cs); in gen3_emit_bb_start()
274 u32 *cs; in gen4_emit_bb_start() local
280 cs = intel_ring_begin(rq, 2); in gen4_emit_bb_start()
281 if (IS_ERR(cs)) in gen4_emit_bb_start()
282 return PTR_ERR(cs); in gen4_emit_bb_start()
284 *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | security; in gen4_emit_bb_start()
285 *cs++ = offset; in gen4_emit_bb_start()
286 intel_ring_advance(rq, cs); in gen4_emit_bb_start()