Lines Matching refs:cs
59 u32 *cs; in gen6_emit_post_sync_nonzero_flush() local
61 cs = intel_ring_begin(rq, 6); in gen6_emit_post_sync_nonzero_flush()
62 if (IS_ERR(cs)) in gen6_emit_post_sync_nonzero_flush()
63 return PTR_ERR(cs); in gen6_emit_post_sync_nonzero_flush()
65 *cs++ = GFX_OP_PIPE_CONTROL(5); in gen6_emit_post_sync_nonzero_flush()
66 *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; in gen6_emit_post_sync_nonzero_flush()
67 *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; in gen6_emit_post_sync_nonzero_flush()
68 *cs++ = 0; /* low dword */ in gen6_emit_post_sync_nonzero_flush()
69 *cs++ = 0; /* high dword */ in gen6_emit_post_sync_nonzero_flush()
70 *cs++ = MI_NOOP; in gen6_emit_post_sync_nonzero_flush()
71 intel_ring_advance(rq, cs); in gen6_emit_post_sync_nonzero_flush()
73 cs = intel_ring_begin(rq, 6); in gen6_emit_post_sync_nonzero_flush()
74 if (IS_ERR(cs)) in gen6_emit_post_sync_nonzero_flush()
75 return PTR_ERR(cs); in gen6_emit_post_sync_nonzero_flush()
77 *cs++ = GFX_OP_PIPE_CONTROL(5); in gen6_emit_post_sync_nonzero_flush()
78 *cs++ = PIPE_CONTROL_QW_WRITE; in gen6_emit_post_sync_nonzero_flush()
79 *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; in gen6_emit_post_sync_nonzero_flush()
80 *cs++ = 0; in gen6_emit_post_sync_nonzero_flush()
81 *cs++ = 0; in gen6_emit_post_sync_nonzero_flush()
82 *cs++ = MI_NOOP; in gen6_emit_post_sync_nonzero_flush()
83 intel_ring_advance(rq, cs); in gen6_emit_post_sync_nonzero_flush()
93 u32 *cs, flags = 0; in gen6_emit_flush_rcs() local
129 cs = intel_ring_begin(rq, 4); in gen6_emit_flush_rcs()
130 if (IS_ERR(cs)) in gen6_emit_flush_rcs()
131 return PTR_ERR(cs); in gen6_emit_flush_rcs()
133 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen6_emit_flush_rcs()
134 *cs++ = flags; in gen6_emit_flush_rcs()
135 *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; in gen6_emit_flush_rcs()
136 *cs++ = 0; in gen6_emit_flush_rcs()
137 intel_ring_advance(rq, cs); in gen6_emit_flush_rcs()
142 u32 *gen6_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs) in gen6_emit_breadcrumb_rcs() argument
145 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen6_emit_breadcrumb_rcs()
146 *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; in gen6_emit_breadcrumb_rcs()
147 *cs++ = 0; in gen6_emit_breadcrumb_rcs()
148 *cs++ = 0; in gen6_emit_breadcrumb_rcs()
150 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen6_emit_breadcrumb_rcs()
151 *cs++ = PIPE_CONTROL_QW_WRITE; in gen6_emit_breadcrumb_rcs()
152 *cs++ = intel_gt_scratch_offset(rq->engine->gt, in gen6_emit_breadcrumb_rcs()
155 *cs++ = 0; in gen6_emit_breadcrumb_rcs()
158 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen6_emit_breadcrumb_rcs()
159 *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | in gen6_emit_breadcrumb_rcs()
164 *cs++ = i915_request_active_seqno(rq) | in gen6_emit_breadcrumb_rcs()
166 *cs++ = rq->fence.seqno; in gen6_emit_breadcrumb_rcs()
168 *cs++ = MI_USER_INTERRUPT; in gen6_emit_breadcrumb_rcs()
169 *cs++ = MI_NOOP; in gen6_emit_breadcrumb_rcs()
171 rq->tail = intel_ring_offset(rq, cs); in gen6_emit_breadcrumb_rcs()
174 return cs; in gen6_emit_breadcrumb_rcs()
179 u32 cmd, *cs; in mi_flush_dw() local
181 cs = intel_ring_begin(rq, 4); in mi_flush_dw()
182 if (IS_ERR(cs)) in mi_flush_dw()
183 return PTR_ERR(cs); in mi_flush_dw()
203 *cs++ = cmd; in mi_flush_dw()
204 *cs++ = HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; in mi_flush_dw()
205 *cs++ = 0; in mi_flush_dw()
206 *cs++ = MI_NOOP; in mi_flush_dw()
208 intel_ring_advance(rq, cs); in mi_flush_dw()
233 u32 *cs; in gen6_emit_bb_start() local
239 cs = intel_ring_begin(rq, 2); in gen6_emit_bb_start()
240 if (IS_ERR(cs)) in gen6_emit_bb_start()
241 return PTR_ERR(cs); in gen6_emit_bb_start()
243 cs = __gen6_emit_bb_start(cs, offset, security); in gen6_emit_bb_start()
244 intel_ring_advance(rq, cs); in gen6_emit_bb_start()
255 u32 *cs; in hsw_emit_bb_start() local
261 cs = intel_ring_begin(rq, 2); in hsw_emit_bb_start()
262 if (IS_ERR(cs)) in hsw_emit_bb_start()
263 return PTR_ERR(cs); in hsw_emit_bb_start()
265 cs = __gen6_emit_bb_start(cs, offset, security); in hsw_emit_bb_start()
266 intel_ring_advance(rq, cs); in hsw_emit_bb_start()
273 u32 *cs; in gen7_stall_cs() local
275 cs = intel_ring_begin(rq, 4); in gen7_stall_cs()
276 if (IS_ERR(cs)) in gen7_stall_cs()
277 return PTR_ERR(cs); in gen7_stall_cs()
279 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen7_stall_cs()
280 *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; in gen7_stall_cs()
281 *cs++ = 0; in gen7_stall_cs()
282 *cs++ = 0; in gen7_stall_cs()
283 intel_ring_advance(rq, cs); in gen7_stall_cs()
293 u32 *cs, flags = 0; in gen7_emit_flush_rcs() local
339 cs = intel_ring_begin(rq, 4); in gen7_emit_flush_rcs()
340 if (IS_ERR(cs)) in gen7_emit_flush_rcs()
341 return PTR_ERR(cs); in gen7_emit_flush_rcs()
343 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen7_emit_flush_rcs()
344 *cs++ = flags; in gen7_emit_flush_rcs()
345 *cs++ = scratch_addr; in gen7_emit_flush_rcs()
346 *cs++ = 0; in gen7_emit_flush_rcs()
347 intel_ring_advance(rq, cs); in gen7_emit_flush_rcs()
352 u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs) in gen7_emit_breadcrumb_rcs() argument
354 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen7_emit_breadcrumb_rcs()
355 *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | in gen7_emit_breadcrumb_rcs()
362 *cs++ = i915_request_active_seqno(rq); in gen7_emit_breadcrumb_rcs()
363 *cs++ = rq->fence.seqno; in gen7_emit_breadcrumb_rcs()
365 *cs++ = MI_USER_INTERRUPT; in gen7_emit_breadcrumb_rcs()
366 *cs++ = MI_NOOP; in gen7_emit_breadcrumb_rcs()
368 rq->tail = intel_ring_offset(rq, cs); in gen7_emit_breadcrumb_rcs()
371 return cs; in gen7_emit_breadcrumb_rcs()
374 u32 *gen6_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs) in gen6_emit_breadcrumb_xcs() argument
379 *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; in gen6_emit_breadcrumb_xcs()
380 *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; in gen6_emit_breadcrumb_xcs()
381 *cs++ = rq->fence.seqno; in gen6_emit_breadcrumb_xcs()
383 *cs++ = MI_USER_INTERRUPT; in gen6_emit_breadcrumb_xcs()
385 rq->tail = intel_ring_offset(rq, cs); in gen6_emit_breadcrumb_xcs()
388 return cs; in gen6_emit_breadcrumb_xcs()
392 u32 *gen7_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs) in gen7_emit_breadcrumb_xcs() argument
399 *cs++ = MI_FLUSH_DW | MI_INVALIDATE_TLB | in gen7_emit_breadcrumb_xcs()
401 *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; in gen7_emit_breadcrumb_xcs()
402 *cs++ = rq->fence.seqno; in gen7_emit_breadcrumb_xcs()
405 *cs++ = MI_STORE_DWORD_INDEX; in gen7_emit_breadcrumb_xcs()
406 *cs++ = I915_GEM_HWS_SEQNO_ADDR; in gen7_emit_breadcrumb_xcs()
407 *cs++ = rq->fence.seqno; in gen7_emit_breadcrumb_xcs()
410 *cs++ = MI_FLUSH_DW; in gen7_emit_breadcrumb_xcs()
411 *cs++ = 0; in gen7_emit_breadcrumb_xcs()
412 *cs++ = 0; in gen7_emit_breadcrumb_xcs()
414 *cs++ = MI_USER_INTERRUPT; in gen7_emit_breadcrumb_xcs()
415 *cs++ = MI_NOOP; in gen7_emit_breadcrumb_xcs()
417 rq->tail = intel_ring_offset(rq, cs); in gen7_emit_breadcrumb_xcs()
420 return cs; in gen7_emit_breadcrumb_xcs()