Lines Matching refs:batch
1370 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch) in gen8_emit_flush_coherentl3_wa() argument
1373 *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; in gen8_emit_flush_coherentl3_wa()
1374 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
1375 *batch++ = intel_gt_scratch_offset(engine->gt, in gen8_emit_flush_coherentl3_wa()
1377 *batch++ = 0; in gen8_emit_flush_coherentl3_wa()
1379 *batch++ = MI_LOAD_REGISTER_IMM(1); in gen8_emit_flush_coherentl3_wa()
1380 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
1381 *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES; in gen8_emit_flush_coherentl3_wa()
1383 batch = gen8_emit_pipe_control(batch, in gen8_emit_flush_coherentl3_wa()
1388 *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; in gen8_emit_flush_coherentl3_wa()
1389 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
1390 *batch++ = intel_gt_scratch_offset(engine->gt, in gen8_emit_flush_coherentl3_wa()
1392 *batch++ = 0; in gen8_emit_flush_coherentl3_wa()
1394 return batch; in gen8_emit_flush_coherentl3_wa()
1412 static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) in gen8_init_indirectctx_bb() argument
1415 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; in gen8_init_indirectctx_bb()
1419 batch = gen8_emit_flush_coherentl3_wa(engine, batch); in gen8_init_indirectctx_bb()
1423 batch = gen8_emit_pipe_control(batch, in gen8_init_indirectctx_bb()
1430 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; in gen8_init_indirectctx_bb()
1433 while ((unsigned long)batch % CACHELINE_BYTES) in gen8_init_indirectctx_bb()
1434 *batch++ = MI_NOOP; in gen8_init_indirectctx_bb()
1442 return batch; in gen8_init_indirectctx_bb()
1450 static u32 *emit_lri(u32 *batch, const struct lri *lri, unsigned int count) in emit_lri() argument
1454 *batch++ = MI_LOAD_REGISTER_IMM(count); in emit_lri()
1456 *batch++ = i915_mmio_reg_offset(lri->reg); in emit_lri()
1457 *batch++ = lri->value; in emit_lri()
1459 *batch++ = MI_NOOP; in emit_lri()
1461 return batch; in emit_lri()
1464 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) in gen9_init_indirectctx_bb() argument
1489 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; in gen9_init_indirectctx_bb()
1492 batch = gen8_emit_flush_coherentl3_wa(engine, batch); in gen9_init_indirectctx_bb()
1495 batch = gen8_emit_pipe_control(batch, in gen9_init_indirectctx_bb()
1502 batch = emit_lri(batch, lri, ARRAY_SIZE(lri)); in gen9_init_indirectctx_bb()
1519 *batch++ = GEN9_MEDIA_POOL_STATE; in gen9_init_indirectctx_bb()
1520 *batch++ = GEN9_MEDIA_POOL_ENABLE; in gen9_init_indirectctx_bb()
1521 *batch++ = 0x00777000; in gen9_init_indirectctx_bb()
1522 *batch++ = 0; in gen9_init_indirectctx_bb()
1523 *batch++ = 0; in gen9_init_indirectctx_bb()
1524 *batch++ = 0; in gen9_init_indirectctx_bb()
1527 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; in gen9_init_indirectctx_bb()
1530 while ((unsigned long)batch % CACHELINE_BYTES) in gen9_init_indirectctx_bb()
1531 *batch++ = MI_NOOP; in gen9_init_indirectctx_bb()
1533 return batch; in gen9_init_indirectctx_bb()
1567 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
1577 void *batch, *batch_ptr; in lrc_init_wa_ctx() local
1625 batch = i915_gem_object_pin_map(wa_ctx->vma->obj, I915_MAP_WB); in lrc_init_wa_ctx()
1626 if (IS_ERR(batch)) { in lrc_init_wa_ctx()
1627 err = PTR_ERR(batch); in lrc_init_wa_ctx()
1636 batch_ptr = batch; in lrc_init_wa_ctx()
1638 wa_bb[i]->offset = batch_ptr - batch; in lrc_init_wa_ctx()
1646 wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset); in lrc_init_wa_ctx()
1648 GEM_BUG_ON(batch_ptr - batch > CTX_WA_BB_SIZE); in lrc_init_wa_ctx()
1650 __i915_gem_object_flush_map(wa_ctx->vma->obj, 0, batch_ptr - batch); in lrc_init_wa_ctx()