Lines Matching refs:pm_iir
126 rps->pm_iir |= GEN6_PM_RP_UP_THRESHOLD; in rps_timer()
131 rps->pm_iir |= GEN6_PM_RP_DOWN_THRESHOLD; in rps_timer()
221 rps->pm_iir = 0; in rps_reset_interrupts()
869 rps->pm_iir = 0; in intel_rps_unpark()
1626 static u32 vlv_wa_c0_ei(struct intel_rps *rps, u32 pm_iir) in vlv_wa_c0_ei() argument
1633 if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0) in vlv_wa_c0_ei()
1673 u32 pm_iir = 0; in rps_work() local
1676 pm_iir = fetch_and_zero(&rps->pm_iir) & rps->pm_events; in rps_work()
1681 if (!pm_iir && !client_boost) in rps_work()
1690 pm_iir |= vlv_wa_c0_ei(rps, pm_iir); in rps_work()
1701 pm_iir, yesno(client_boost), in rps_work()
1707 } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { in rps_work()
1717 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { in rps_work()
1723 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { in rps_work()
1756 void gen11_rps_irq_handler(struct intel_rps *rps, u32 pm_iir) in gen11_rps_irq_handler() argument
1759 const u32 events = rps->pm_events & pm_iir; in gen11_rps_irq_handler()
1770 rps->pm_iir |= events; in gen11_rps_irq_handler()
1774 void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir) in gen6_rps_irq_handler() argument
1779 events = pm_iir & rps->pm_events; in gen6_rps_irq_handler()
1786 rps->pm_iir |= events; in gen6_rps_irq_handler()
1795 if (pm_iir & PM_VEBOX_USER_INTERRUPT) in gen6_rps_irq_handler()
1796 intel_engine_cs_irq(gt->engine[VECS0], pm_iir >> 10); in gen6_rps_irq_handler()
1798 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) in gen6_rps_irq_handler()
1799 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir); in gen6_rps_irq_handler()