Lines Matching refs:gt
217 struct intel_gt *gt = arg; in live_rps_clock_interval() local
218 struct intel_rps *rps = >->rps; in live_rps_clock_interval()
225 if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6) in live_rps_clock_interval()
228 if (igt_spinner_init(&spin, gt)) in live_rps_clock_interval()
231 intel_gt_pm_wait_for_idle(gt); in live_rps_clock_interval()
235 intel_gt_pm_get(gt); in live_rps_clock_interval()
236 intel_rps_disable(>->rps); in live_rps_clock_interval()
238 intel_gt_check_clock_frequency(gt); in live_rps_clock_interval()
240 for_each_engine(engine, gt, id) { in live_rps_clock_interval()
266 intel_gt_set_wedged(engine->gt); in live_rps_clock_interval()
271 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL); in live_rps_clock_interval()
273 intel_uncore_write_fw(gt->uncore, GEN6_RP_CUR_UP_EI, 0); in live_rps_clock_interval()
276 intel_uncore_write_fw(gt->uncore, in live_rps_clock_interval()
278 intel_uncore_write_fw(gt->uncore, in live_rps_clock_interval()
281 intel_uncore_write_fw(gt->uncore, GEN6_RP_CONTROL, in live_rps_clock_interval()
284 if (wait_for(intel_uncore_read_fw(gt->uncore, in live_rps_clock_interval()
300 cycles_[i] = -intel_uncore_read_fw(gt->uncore, GEN6_RP_CUR_UP_EI); in live_rps_clock_interval()
305 cycles_[i] += intel_uncore_read_fw(gt->uncore, GEN6_RP_CUR_UP_EI); in live_rps_clock_interval()
317 intel_uncore_write_fw(gt->uncore, GEN6_RP_CONTROL, 0); in live_rps_clock_interval()
318 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL); in live_rps_clock_interval()
324 u64 time = intel_gt_pm_interval_to_ns(gt, cycles); in live_rps_clock_interval()
326 intel_gt_ns_to_pm_interval(gt, dt); in live_rps_clock_interval()
330 gt->clock_frequency / 1000); in live_rps_clock_interval()
347 if (igt_flush_test(gt->i915)) in live_rps_clock_interval()
353 intel_rps_enable(>->rps); in live_rps_clock_interval()
354 intel_gt_pm_put(gt); in live_rps_clock_interval()
358 intel_gt_pm_wait_for_idle(gt); in live_rps_clock_interval()
369 struct intel_gt *gt = arg; in live_rps_control() local
370 struct intel_rps *rps = >->rps; in live_rps_control()
387 if (IS_CHERRYVIEW(gt->i915)) /* XXX fragile PCU */ in live_rps_control()
390 if (igt_spinner_init(&spin, gt)) in live_rps_control()
393 intel_gt_pm_wait_for_idle(gt); in live_rps_control()
397 intel_gt_pm_get(gt); in live_rps_control()
398 for_each_engine(engine, gt, id) { in live_rps_control()
424 intel_gt_set_wedged(engine->gt); in live_rps_control()
482 if (igt_flush_test(gt->i915)) { in live_rps_control()
487 intel_gt_pm_put(gt); in live_rps_control()
491 intel_gt_pm_wait_for_idle(gt); in live_rps_control()
601 struct intel_gt *gt = arg; in live_rps_frequency_cs() local
602 struct intel_rps *rps = >->rps; in live_rps_frequency_cs()
617 if (GRAPHICS_VER(gt->i915) < 8) /* for CS simplicity */ in live_rps_frequency_cs()
623 intel_gt_pm_wait_for_idle(gt); in live_rps_frequency_cs()
627 for_each_engine(engine, gt, id) { in live_rps_frequency_cs()
724 if (igt_flush_test(gt->i915)) in live_rps_frequency_cs()
730 intel_gt_pm_wait_for_idle(gt); in live_rps_frequency_cs()
742 struct intel_gt *gt = arg; in live_rps_frequency_srm() local
743 struct intel_rps *rps = >->rps; in live_rps_frequency_srm()
758 if (GRAPHICS_VER(gt->i915) < 8) /* for CS simplicity */ in live_rps_frequency_srm()
764 intel_gt_pm_wait_for_idle(gt); in live_rps_frequency_srm()
768 for_each_engine(engine, gt, id) { in live_rps_frequency_srm()
864 if (igt_flush_test(gt->i915)) in live_rps_frequency_srm()
870 intel_gt_pm_wait_for_idle(gt); in live_rps_frequency_srm()
917 intel_gt_set_wedged(engine->gt); in __rps_up_interrupt()
944 timeout = intel_gt_pm_interval_to_ns(engine->gt, timeout); in __rps_up_interrupt()
992 timeout = intel_gt_pm_interval_to_ns(engine->gt, timeout); in __rps_down_interrupt()
1021 struct intel_gt *gt = arg; in live_rps_interrupt() local
1022 struct intel_rps *rps = >->rps; in live_rps_interrupt()
1034 if (!intel_rps_has_interrupts(rps) || GRAPHICS_VER(gt->i915) < 6) in live_rps_interrupt()
1037 intel_gt_pm_get(gt); in live_rps_interrupt()
1039 intel_gt_pm_put(gt); in live_rps_interrupt()
1045 if (igt_spinner_init(&spin, gt)) in live_rps_interrupt()
1048 intel_gt_pm_wait_for_idle(gt); in live_rps_interrupt()
1052 for_each_engine(engine, gt, id) { in live_rps_interrupt()
1055 intel_gt_pm_wait_for_idle(engine->gt); in live_rps_interrupt()
1066 intel_gt_pm_wait_for_idle(engine->gt); in live_rps_interrupt()
1072 intel_rc6_disable(>->rc6); in live_rps_interrupt()
1076 intel_rc6_enable(>->rc6); in live_rps_interrupt()
1084 if (igt_flush_test(gt->i915)) in live_rps_interrupt()
1089 intel_gt_pm_wait_for_idle(gt); in live_rps_interrupt()
1125 struct intel_gt *gt = arg; in live_rps_power() local
1126 struct intel_rps *rps = >->rps; in live_rps_power()
1139 if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6) in live_rps_power()
1142 if (!librapl_supported(gt->i915)) in live_rps_power()
1145 if (igt_spinner_init(&spin, gt)) in live_rps_power()
1148 intel_gt_pm_wait_for_idle(gt); in live_rps_power()
1152 for_each_engine(engine, gt, id) { in live_rps_power()
1180 intel_gt_set_wedged(engine->gt); in live_rps_power()
1213 if (igt_flush_test(gt->i915)) { in live_rps_power()
1221 intel_gt_pm_wait_for_idle(gt); in live_rps_power()
1229 struct intel_gt *gt = arg; in live_rps_dynamic() local
1230 struct intel_rps *rps = >->rps; in live_rps_dynamic()
1243 if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6) in live_rps_dynamic()
1246 if (igt_spinner_init(&spin, gt)) in live_rps_dynamic()
1254 for_each_engine(engine, gt, id) { in live_rps_dynamic()
1264 intel_gt_pm_wait_for_idle(gt); in live_rps_dynamic()
1269 intel_rc6_disable(>->rc6); in live_rps_dynamic()
1305 intel_rc6_enable(>->rc6); in live_rps_dynamic()
1308 if (igt_flush_test(gt->i915)) in live_rps_dynamic()