Lines Matching refs:guc
77 void (*reset)(struct intel_guc *guc);
78 void (*enable)(struct intel_guc *guc);
79 void (*disable)(struct intel_guc *guc);
183 inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len) in intel_guc_send() argument
185 return intel_guc_ct_send(&guc->ct, action, len, NULL, 0, 0); in intel_guc_send()
189 inline int intel_guc_send_nb(struct intel_guc *guc, const u32 *action, u32 len, in intel_guc_send_nb() argument
192 return intel_guc_ct_send(&guc->ct, action, len, NULL, 0, in intel_guc_send_nb()
197 intel_guc_send_and_receive(struct intel_guc *guc, const u32 *action, u32 len, in intel_guc_send_and_receive() argument
200 return intel_guc_ct_send(&guc->ct, action, len, in intel_guc_send_and_receive()
204 static inline int intel_guc_send_busy_loop(struct intel_guc *guc, in intel_guc_send_busy_loop() argument
225 err = intel_guc_send_nb(guc, action, len, g2h_len_dw); in intel_guc_send_busy_loop()
240 static inline void intel_guc_to_host_event_handler(struct intel_guc *guc) in intel_guc_to_host_event_handler() argument
242 intel_guc_ct_event_handler(&guc->ct); in intel_guc_to_host_event_handler()
261 static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc, in intel_guc_ggtt_offset() argument
272 void intel_guc_init_early(struct intel_guc *guc);
273 void intel_guc_init_late(struct intel_guc *guc);
274 void intel_guc_init_send_regs(struct intel_guc *guc);
275 void intel_guc_write_params(struct intel_guc *guc);
276 int intel_guc_init(struct intel_guc *guc);
277 void intel_guc_fini(struct intel_guc *guc);
278 void intel_guc_notify(struct intel_guc *guc);
279 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
281 int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
283 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
284 int intel_guc_suspend(struct intel_guc *guc);
285 int intel_guc_resume(struct intel_guc *guc);
286 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
287 int intel_guc_allocate_and_map_vma(struct intel_guc *guc, u32 size,
290 static inline bool intel_guc_is_supported(struct intel_guc *guc) in intel_guc_is_supported() argument
292 return intel_uc_fw_is_supported(&guc->fw); in intel_guc_is_supported()
295 static inline bool intel_guc_is_wanted(struct intel_guc *guc) in intel_guc_is_wanted() argument
297 return intel_uc_fw_is_enabled(&guc->fw); in intel_guc_is_wanted()
300 static inline bool intel_guc_is_used(struct intel_guc *guc) in intel_guc_is_used() argument
302 GEM_BUG_ON(__intel_uc_fw_status(&guc->fw) == INTEL_UC_FIRMWARE_SELECTED); in intel_guc_is_used()
303 return intel_uc_fw_is_available(&guc->fw); in intel_guc_is_used()
306 static inline bool intel_guc_is_fw_running(struct intel_guc *guc) in intel_guc_is_fw_running() argument
308 return intel_uc_fw_is_running(&guc->fw); in intel_guc_is_fw_running()
311 static inline bool intel_guc_is_ready(struct intel_guc *guc) in intel_guc_is_ready() argument
313 return intel_guc_is_fw_running(guc) && intel_guc_ct_enabled(&guc->ct); in intel_guc_is_ready()
316 static inline void intel_guc_reset_interrupts(struct intel_guc *guc) in intel_guc_reset_interrupts() argument
318 guc->interrupts.reset(guc); in intel_guc_reset_interrupts()
321 static inline void intel_guc_enable_interrupts(struct intel_guc *guc) in intel_guc_enable_interrupts() argument
323 guc->interrupts.enable(guc); in intel_guc_enable_interrupts()
326 static inline void intel_guc_disable_interrupts(struct intel_guc *guc) in intel_guc_disable_interrupts() argument
328 guc->interrupts.disable(guc); in intel_guc_disable_interrupts()
331 static inline int intel_guc_sanitize(struct intel_guc *guc) in intel_guc_sanitize() argument
333 intel_uc_fw_sanitize(&guc->fw); in intel_guc_sanitize()
334 intel_guc_disable_interrupts(guc); in intel_guc_sanitize()
335 intel_guc_ct_sanitize(&guc->ct); in intel_guc_sanitize()
336 guc->mmio_msg = 0; in intel_guc_sanitize()
341 static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask) in intel_guc_enable_msg() argument
343 spin_lock_irq(&guc->irq_lock); in intel_guc_enable_msg()
344 guc->msg_enabled_mask |= mask; in intel_guc_enable_msg()
345 spin_unlock_irq(&guc->irq_lock); in intel_guc_enable_msg()
348 static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask) in intel_guc_disable_msg() argument
350 spin_lock_irq(&guc->irq_lock); in intel_guc_disable_msg()
351 guc->msg_enabled_mask &= ~mask; in intel_guc_disable_msg()
352 spin_unlock_irq(&guc->irq_lock); in intel_guc_disable_msg()
355 int intel_guc_wait_for_idle(struct intel_guc *guc, long timeout);
357 int intel_guc_deregister_done_process_msg(struct intel_guc *guc,
359 int intel_guc_sched_done_process_msg(struct intel_guc *guc,
361 int intel_guc_context_reset_process_msg(struct intel_guc *guc,
363 int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
368 int intel_guc_global_policies_update(struct intel_guc *guc);
372 void intel_guc_submission_reset_prepare(struct intel_guc *guc);
373 void intel_guc_submission_reset(struct intel_guc *guc, bool stalled);
374 void intel_guc_submission_reset_finish(struct intel_guc *guc);
375 void intel_guc_submission_cancel_requests(struct intel_guc *guc);
377 void intel_guc_load_status(struct intel_guc *guc, struct drm_printer *p);
379 void intel_guc_write_barrier(struct intel_guc *guc);