Lines Matching refs:vgpu_vreg_t

62 	if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))  in edp_pipe_is_enabled()
78 if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE) in pipe_is_enabled()
180 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= in emulate_monitor_status_change()
186 vgpu_vreg_t(vgpu, PIPECONF(pipe)) &= in emulate_monitor_status_change()
188 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE; in emulate_monitor_status_change()
189 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; in emulate_monitor_status_change()
190 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE; in emulate_monitor_status_change()
191 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE; in emulate_monitor_status_change()
195 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(trans)) &= in emulate_monitor_status_change()
199 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= in emulate_monitor_status_change()
204 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &= in emulate_monitor_status_change()
206 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |= in emulate_monitor_status_change()
210 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &= in emulate_monitor_status_change()
215 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &= in emulate_monitor_status_change()
218 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE; in emulate_monitor_status_change()
220 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= in emulate_monitor_status_change()
222 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= in emulate_monitor_status_change()
224 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= in emulate_monitor_status_change()
227 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK; in emulate_monitor_status_change()
228 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK; in emulate_monitor_status_change()
230 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1)); in emulate_monitor_status_change()
231 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= in emulate_monitor_status_change()
233 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= in emulate_monitor_status_change()
235 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30); in emulate_monitor_status_change()
236 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30); in emulate_monitor_status_change()
238 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED; in emulate_monitor_status_change()
239 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED; in emulate_monitor_status_change()
247 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; in emulate_monitor_status_change()
248 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= I965_PIPECONF_ACTIVE; in emulate_monitor_status_change()
256 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT; in emulate_monitor_status_change()
257 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e; in emulate_monitor_status_change()
258 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000; in emulate_monitor_status_change()
259 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; in emulate_monitor_status_change()
260 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; in emulate_monitor_status_change()
264 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1); in emulate_monitor_status_change()
265 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= in emulate_monitor_status_change()
267 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |= in emulate_monitor_status_change()
269 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= in emulate_monitor_status_change()
271 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= in emulate_monitor_status_change()
274 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |= in emulate_monitor_status_change()
278 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= in emulate_monitor_status_change()
280 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &= in emulate_monitor_status_change()
282 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |= in emulate_monitor_status_change()
285 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= in emulate_monitor_status_change()
287 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= in emulate_monitor_status_change()
292 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; in emulate_monitor_status_change()
293 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0); in emulate_monitor_status_change()
294 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= in emulate_monitor_status_change()
296 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= in emulate_monitor_status_change()
298 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |= in emulate_monitor_status_change()
300 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &= in emulate_monitor_status_change()
303 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |= in emulate_monitor_status_change()
307 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= in emulate_monitor_status_change()
309 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= in emulate_monitor_status_change()
311 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= in emulate_monitor_status_change()
315 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= in emulate_monitor_status_change()
317 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= in emulate_monitor_status_change()
322 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; in emulate_monitor_status_change()
323 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0); in emulate_monitor_status_change()
324 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= in emulate_monitor_status_change()
326 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= in emulate_monitor_status_change()
328 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |= in emulate_monitor_status_change()
330 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &= in emulate_monitor_status_change()
333 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |= in emulate_monitor_status_change()
337 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= in emulate_monitor_status_change()
339 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= in emulate_monitor_status_change()
341 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= in emulate_monitor_status_change()
345 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= in emulate_monitor_status_change()
347 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= in emulate_monitor_status_change()
354 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT | in emulate_monitor_status_change()
362 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT | in emulate_monitor_status_change()
364 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |= in emulate_monitor_status_change()
377 vgpu_vreg_t(vgpu, DPLL_CTRL1) = in emulate_monitor_status_change()
379 vgpu_vreg_t(vgpu, DPLL_CTRL1) |= in emulate_monitor_status_change()
381 vgpu_vreg_t(vgpu, LCPLL1_CTL) = in emulate_monitor_status_change()
383 vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0); in emulate_monitor_status_change()
390 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT; in emulate_monitor_status_change()
391 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e; in emulate_monitor_status_change()
392 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000; in emulate_monitor_status_change()
393 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; in emulate_monitor_status_change()
394 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; in emulate_monitor_status_change()
398 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= in emulate_monitor_status_change()
400 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= in emulate_monitor_status_change()
402 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= in emulate_monitor_status_change()
404 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; in emulate_monitor_status_change()
405 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= in emulate_monitor_status_change()
408 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= in emulate_monitor_status_change()
413 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &= in emulate_monitor_status_change()
415 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |= in emulate_monitor_status_change()
418 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE; in emulate_monitor_status_change()
419 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE; in emulate_monitor_status_change()
420 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT; in emulate_monitor_status_change()
424 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= in emulate_monitor_status_change()
426 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= in emulate_monitor_status_change()
428 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= in emulate_monitor_status_change()
430 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT; in emulate_monitor_status_change()
431 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= in emulate_monitor_status_change()
434 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= in emulate_monitor_status_change()
439 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &= in emulate_monitor_status_change()
441 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |= in emulate_monitor_status_change()
444 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE; in emulate_monitor_status_change()
445 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE; in emulate_monitor_status_change()
446 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; in emulate_monitor_status_change()
450 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= in emulate_monitor_status_change()
452 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= in emulate_monitor_status_change()
454 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= in emulate_monitor_status_change()
456 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; in emulate_monitor_status_change()
457 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= in emulate_monitor_status_change()
460 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= in emulate_monitor_status_change()
465 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &= in emulate_monitor_status_change()
467 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |= in emulate_monitor_status_change()
470 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE; in emulate_monitor_status_change()
471 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE; in emulate_monitor_status_change()
472 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; in emulate_monitor_status_change()
480 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT; in emulate_monitor_status_change()
485 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= in emulate_monitor_status_change()
488 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT; in emulate_monitor_status_change()
490 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED; in emulate_monitor_status_change()
495 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK; in emulate_monitor_status_change()
499 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE; in emulate_monitor_status_change()
500 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; in emulate_monitor_status_change()
501 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE; in emulate_monitor_status_change()
502 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE; in emulate_monitor_status_change()
505 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; in emulate_monitor_status_change()
642 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++; in emulate_vblank_on_pipe()
675 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= in intel_vgpu_emulate_hotplug()
677 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; in intel_vgpu_emulate_hotplug()
679 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= in intel_vgpu_emulate_hotplug()
681 vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT; in intel_vgpu_emulate_hotplug()
683 vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT; in intel_vgpu_emulate_hotplug()
684 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= in intel_vgpu_emulate_hotplug()
690 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= in intel_vgpu_emulate_hotplug()
693 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= in intel_vgpu_emulate_hotplug()
696 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= in intel_vgpu_emulate_hotplug()
698 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= in intel_vgpu_emulate_hotplug()
700 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= in intel_vgpu_emulate_hotplug()
706 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= in intel_vgpu_emulate_hotplug()
708 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= in intel_vgpu_emulate_hotplug()
711 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= in intel_vgpu_emulate_hotplug()
713 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= in intel_vgpu_emulate_hotplug()
716 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= in intel_vgpu_emulate_hotplug()
718 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= in intel_vgpu_emulate_hotplug()
720 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= in intel_vgpu_emulate_hotplug()
726 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= in intel_vgpu_emulate_hotplug()
728 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= in intel_vgpu_emulate_hotplug()
731 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= in intel_vgpu_emulate_hotplug()
733 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= in intel_vgpu_emulate_hotplug()
736 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= in intel_vgpu_emulate_hotplug()
738 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= in intel_vgpu_emulate_hotplug()
740 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= in intel_vgpu_emulate_hotplug()