Lines Matching refs:vgpu_vreg_t
249 vgpu_vreg_t(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0; in intel_vgpu_reset_mmio()
252 vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0; in intel_vgpu_reset_mmio()
255 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; in intel_vgpu_reset_mmio()
258 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= in intel_vgpu_reset_mmio()
260 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= in intel_vgpu_reset_mmio()
262 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= in intel_vgpu_reset_mmio()
264 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= in intel_vgpu_reset_mmio()
266 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= in intel_vgpu_reset_mmio()
268 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= in intel_vgpu_reset_mmio()
270 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= in intel_vgpu_reset_mmio()
273 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &= in intel_vgpu_reset_mmio()
275 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |= in intel_vgpu_reset_mmio()
278 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &= in intel_vgpu_reset_mmio()
280 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |= in intel_vgpu_reset_mmio()
283 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |= in intel_vgpu_reset_mmio()