xref: /linux/drivers/gpu/drm/i915/i915_irq.c

182 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)  in intel_hpd_init_pins()  argument
184 	struct i915_hotplug *hpd = &dev_priv->hotplug;  in intel_hpd_init_pins()
186 	if (HAS_GMCH(dev_priv)) {  in intel_hpd_init_pins()
187 		if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||  in intel_hpd_init_pins()
188 		    IS_CHERRYVIEW(dev_priv))  in intel_hpd_init_pins()
195 	if (DISPLAY_VER(dev_priv) >= 11)  in intel_hpd_init_pins()
197 	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))  in intel_hpd_init_pins()
199 	else if (DISPLAY_VER(dev_priv) >= 8)  in intel_hpd_init_pins()
201 	else if (DISPLAY_VER(dev_priv) >= 7)  in intel_hpd_init_pins()
206 	if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) &&  in intel_hpd_init_pins()
207 	    (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))  in intel_hpd_init_pins()
210 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)  in intel_hpd_init_pins()
212 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)  in intel_hpd_init_pins()
214 	else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))  in intel_hpd_init_pins()
216 	else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_CPT(dev_priv))  in intel_hpd_init_pins()
218 	else if (HAS_PCH_IBX(dev_priv))  in intel_hpd_init_pins()
221 		MISSING_CASE(INTEL_PCH_TYPE(dev_priv));  in intel_hpd_init_pins()
225 intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)  in intel_handle_vblank()  argument
227 	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);  in intel_handle_vblank()
320 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,  in i915_hotplug_interrupt_update_locked()  argument
326 	lockdep_assert_held(&dev_priv->irq_lock);  in i915_hotplug_interrupt_update_locked()
327 	drm_WARN_ON(&dev_priv->drm, bits & ~mask);  in i915_hotplug_interrupt_update_locked()
329 	val = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_EN);  in i915_hotplug_interrupt_update_locked()
332 	intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_EN, val);  in i915_hotplug_interrupt_update_locked()
347 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,  in i915_hotplug_interrupt_update()  argument
351 	spin_lock_irq(&dev_priv->irq_lock);  in i915_hotplug_interrupt_update()
352 	i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);  in i915_hotplug_interrupt_update()
353 	spin_unlock_irq(&dev_priv->irq_lock);  in i915_hotplug_interrupt_update()
362 static void ilk_update_display_irq(struct drm_i915_private *dev_priv,  in ilk_update_display_irq()  argument
367 	lockdep_assert_held(&dev_priv->irq_lock);  in ilk_update_display_irq()
368 	drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);  in ilk_update_display_irq()
370 	new_val = dev_priv->irq_mask;  in ilk_update_display_irq()
374 	if (new_val != dev_priv->irq_mask &&  in ilk_update_display_irq()
375 	    !drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) {  in ilk_update_display_irq()
376 		dev_priv->irq_mask = new_val;  in ilk_update_display_irq()
377 		intel_uncore_write(&dev_priv->uncore, DEIMR, dev_priv->irq_mask);  in ilk_update_display_irq()
378 		intel_uncore_posting_read(&dev_priv->uncore, DEIMR);  in ilk_update_display_irq()
398 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,  in bdw_update_port_irq()  argument
405 	lockdep_assert_held(&dev_priv->irq_lock);  in bdw_update_port_irq()
407 	drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);  in bdw_update_port_irq()
409 	if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))  in bdw_update_port_irq()
412 	old_val = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IMR);  in bdw_update_port_irq()
419 		intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IMR, new_val);  in bdw_update_port_irq()
420 		intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PORT_IMR);  in bdw_update_port_irq()
431 static void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,  in bdw_update_pipe_irq()  argument
437 	lockdep_assert_held(&dev_priv->irq_lock);  in bdw_update_pipe_irq()
439 	drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);  in bdw_update_pipe_irq()
441 	if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))  in bdw_update_pipe_irq()
444 	new_val = dev_priv->de_irq_mask[pipe];  in bdw_update_pipe_irq()
448 	if (new_val != dev_priv->de_irq_mask[pipe]) {  in bdw_update_pipe_irq()
449 		dev_priv->de_irq_mask[pipe] = new_val;  in bdw_update_pipe_irq()
450 		intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);  in bdw_update_pipe_irq()
451 		intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe));  in bdw_update_pipe_irq()
473 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,  in ibx_display_interrupt_update()  argument
477 	u32 sdeimr = intel_uncore_read(&dev_priv->uncore, SDEIMR);  in ibx_display_interrupt_update()
481 	drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);  in ibx_display_interrupt_update()
483 	lockdep_assert_held(&dev_priv->irq_lock);  in ibx_display_interrupt_update()
485 	if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))  in ibx_display_interrupt_update()
488 	intel_uncore_write(&dev_priv->uncore, SDEIMR, sdeimr);  in ibx_display_interrupt_update()
489 	intel_uncore_posting_read(&dev_priv->uncore, SDEIMR);  in ibx_display_interrupt_update()
502 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,  in i915_pipestat_enable_mask()  argument
505 	u32 status_mask = dev_priv->pipestat_irq_mask[pipe];  in i915_pipestat_enable_mask()
508 	lockdep_assert_held(&dev_priv->irq_lock);  in i915_pipestat_enable_mask()
510 	if (DISPLAY_VER(dev_priv) < 5)  in i915_pipestat_enable_mask()
517 	if (drm_WARN_ON_ONCE(&dev_priv->drm,  in i915_pipestat_enable_mask()
524 	if (drm_WARN_ON_ONCE(&dev_priv->drm,  in i915_pipestat_enable_mask()
537 	drm_WARN_ONCE(&dev_priv->drm,  in i915_pipestat_enable_mask()
546 void i915_enable_pipestat(struct drm_i915_private *dev_priv,  in i915_enable_pipestat()  argument
552 	drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,  in i915_enable_pipestat()
556 	lockdep_assert_held(&dev_priv->irq_lock);  in i915_enable_pipestat()
557 	drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));  in i915_enable_pipestat()
559 	if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)  in i915_enable_pipestat()
562 	dev_priv->pipestat_irq_mask[pipe] |= status_mask;  in i915_enable_pipestat()
563 	enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);  in i915_enable_pipestat()
565 	intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask);  in i915_enable_pipestat()
566 	intel_uncore_posting_read(&dev_priv->uncore, reg);  in i915_enable_pipestat()
569 void i915_disable_pipestat(struct drm_i915_private *dev_priv,  in i915_disable_pipestat()  argument
575 	drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,  in i915_disable_pipestat()
579 	lockdep_assert_held(&dev_priv->irq_lock);  in i915_disable_pipestat()
580 	drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));  in i915_disable_pipestat()
582 	if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)  in i915_disable_pipestat()
585 	dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;  in i915_disable_pipestat()
586 	enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);  in i915_disable_pipestat()
588 	intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask);  in i915_disable_pipestat()
589 	intel_uncore_posting_read(&dev_priv->uncore, reg);  in i915_disable_pipestat()
592 static bool i915_has_asle(struct drm_i915_private *dev_priv)  in i915_has_asle()  argument
594 	if (!dev_priv->opregion.asle)  in i915_has_asle()
597 	return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);  in i915_has_asle()
604 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)  in i915_enable_asle_pipestat()  argument
606 	if (!i915_has_asle(dev_priv))  in i915_enable_asle_pipestat()
609 	spin_lock_irq(&dev_priv->irq_lock);  in i915_enable_asle_pipestat()
611 	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);  in i915_enable_asle_pipestat()
612 	if (DISPLAY_VER(dev_priv) >= 4)  in i915_enable_asle_pipestat()
613 		i915_enable_pipestat(dev_priv, PIPE_A,  in i915_enable_asle_pipestat()
616 	spin_unlock_irq(&dev_priv->irq_lock);  in i915_enable_asle_pipestat()
674 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);  in i915_get_vblank_counter()  local
675 	struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];  in i915_get_vblank_counter()
711 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);  in i915_get_vblank_counter()
719 		high1 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;  in i915_get_vblank_counter()
720 		low   = intel_de_read_fw(dev_priv, low_frame);  in i915_get_vblank_counter()
721 		high2 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;  in i915_get_vblank_counter()
724 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);  in i915_get_vblank_counter()
740 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);  in g4x_get_vblank_counter()  local
741 	struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];  in g4x_get_vblank_counter()
747 	return intel_uncore_read(&dev_priv->uncore, PIPE_FRMCOUNT_G4X(pipe));  in g4x_get_vblank_counter()
752 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_scanlines_since_frame_timestamp()  local
772 		scan_prev_time = intel_de_read_fw(dev_priv,  in intel_crtc_scanlines_since_frame_timestamp()
779 		scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR);  in intel_crtc_scanlines_since_frame_timestamp()
781 		scan_post_time = intel_de_read_fw(dev_priv,  in intel_crtc_scanlines_since_frame_timestamp()
820 	struct drm_i915_private *dev_priv = to_i915(dev);  in __intel_get_crtc_scanline()  local
839 	if (DISPLAY_VER(dev_priv) == 2)  in __intel_get_crtc_scanline()
840 		position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;  in __intel_get_crtc_scanline()
842 		position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;  in __intel_get_crtc_scanline()
856 	if (HAS_DDI(dev_priv) && !position) {  in __intel_get_crtc_scanline()
861 			temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;  in __intel_get_crtc_scanline()
883 	struct drm_i915_private *dev_priv = to_i915(dev);  in i915_get_crtc_scanoutpos()  local
889 	bool use_scanline_counter = DISPLAY_VER(dev_priv) >= 5 ||  in i915_get_crtc_scanoutpos()
890 		IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) == 2 ||  in i915_get_crtc_scanoutpos()
893 	if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) {  in i915_get_crtc_scanoutpos()
894 		drm_dbg(&dev_priv->drm,  in i915_get_crtc_scanoutpos()
917 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);  in i915_get_crtc_scanoutpos()
948 …position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIF…  in i915_get_crtc_scanoutpos()
985 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);  in i915_get_crtc_scanoutpos()
1019 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_get_crtc_scanline()  local
1023 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);  in intel_get_crtc_scanline()
1025 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);  in intel_get_crtc_scanline()
1041 	struct drm_i915_private *dev_priv =  in ivb_parity_work()  local
1042 		container_of(work, typeof(*dev_priv), l3_parity.error_work);  in ivb_parity_work()
1043 	struct intel_gt *gt = &dev_priv->gt;  in ivb_parity_work()
1053 	mutex_lock(&dev_priv->drm.struct_mutex);  in ivb_parity_work()
1056 	if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice))  in ivb_parity_work()
1059 	misccpctl = intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL);  in ivb_parity_work()
1060 	intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);  in ivb_parity_work()
1061 	intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL);  in ivb_parity_work()
1063 	while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {  in ivb_parity_work()
1067 		if (drm_WARN_ON_ONCE(&dev_priv->drm,  in ivb_parity_work()
1068 				     slice >= NUM_L3_SLICES(dev_priv)))  in ivb_parity_work()
1071 		dev_priv->l3_parity.which_slice &= ~(1<<slice);  in ivb_parity_work()
1075 		error_status = intel_uncore_read(&dev_priv->uncore, reg);  in ivb_parity_work()
1080 		intel_uncore_write(&dev_priv->uncore, reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);  in ivb_parity_work()
1081 		intel_uncore_posting_read(&dev_priv->uncore, reg);  in ivb_parity_work()
1090 		kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,  in ivb_parity_work()
1102 	intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl);  in ivb_parity_work()
1105 	drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice);  in ivb_parity_work()
1107 	gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv));  in ivb_parity_work()
1110 	mutex_unlock(&dev_priv->drm.struct_mutex);  in ivb_parity_work()
1241 static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,  in intel_get_hpd_pins()  argument
1261 	drm_dbg(&dev_priv->drm,  in intel_get_hpd_pins()
1267 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,  in intel_hpd_enabled_irqs()  argument
1273 	for_each_intel_encoder(&dev_priv->drm, encoder)  in intel_hpd_enabled_irqs()
1274 		if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)  in intel_hpd_enabled_irqs()
1280 static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,  in intel_hpd_hotplug_irqs()  argument
1286 	for_each_intel_encoder(&dev_priv->drm, encoder)  in intel_hpd_hotplug_irqs()
1304 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)  in gmbus_irq_handler()  argument
1306 	wake_up_all(&dev_priv->gmbus_wait_queue);  in gmbus_irq_handler()
1309 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)  in dp_aux_irq_handler()  argument
1311 	wake_up_all(&dev_priv->gmbus_wait_queue);  in dp_aux_irq_handler()
1315 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,  in display_pipe_crc_irq_handler()  argument
1321 	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);  in display_pipe_crc_irq_handler()
1337 	    (DISPLAY_VER(dev_priv) >= 8 && pipe_crc->skipped == 1)) {  in display_pipe_crc_irq_handler()
1350 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,  in display_pipe_crc_irq_handler()  argument
1375 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,  in hsw_pipe_crc_irq_handler()  argument
1378 	display_pipe_crc_irq_handler(dev_priv, pipe,  in hsw_pipe_crc_irq_handler()
1379 				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)),  in hsw_pipe_crc_irq_handler()
1383 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,  in ivb_pipe_crc_irq_handler()  argument
1386 	display_pipe_crc_irq_handler(dev_priv, pipe,  in ivb_pipe_crc_irq_handler()
1387 				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)),  in ivb_pipe_crc_irq_handler()
1388 				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)),  in ivb_pipe_crc_irq_handler()
1389 				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)),  in ivb_pipe_crc_irq_handler()
1390 				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)),  in ivb_pipe_crc_irq_handler()
1391 				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe)));  in ivb_pipe_crc_irq_handler()
1394 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,  in i9xx_pipe_crc_irq_handler()  argument
1399 	if (DISPLAY_VER(dev_priv) >= 3)  in i9xx_pipe_crc_irq_handler()
1400 		res1 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES1_I915(pipe));  in i9xx_pipe_crc_irq_handler()
1404 	if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))  in i9xx_pipe_crc_irq_handler()
1405 		res2 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES2_G4X(pipe));  in i9xx_pipe_crc_irq_handler()
1409 	display_pipe_crc_irq_handler(dev_priv, pipe,  in i9xx_pipe_crc_irq_handler()
1410 				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(pipe)),  in i9xx_pipe_crc_irq_handler()
1411 				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(pipe)),  in i9xx_pipe_crc_irq_handler()
1412 				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(pipe)),  in i9xx_pipe_crc_irq_handler()
1416 static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)  in i9xx_pipestat_irq_reset()  argument
1420 	for_each_pipe(dev_priv, pipe) {  in i9xx_pipestat_irq_reset()
1421 		intel_uncore_write(&dev_priv->uncore, PIPESTAT(pipe),  in i9xx_pipestat_irq_reset()
1425 		dev_priv->pipestat_irq_mask[pipe] = 0;  in i9xx_pipestat_irq_reset()
1429 static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,  in i9xx_pipestat_irq_ack()  argument
1434 	spin_lock(&dev_priv->irq_lock);  in i9xx_pipestat_irq_ack()
1436 	if (!dev_priv->display_irqs_enabled) {  in i9xx_pipestat_irq_ack()
1437 		spin_unlock(&dev_priv->irq_lock);  in i9xx_pipestat_irq_ack()
1441 	for_each_pipe(dev_priv, pipe) {  in i9xx_pipestat_irq_ack()
1469 			status_mask |= dev_priv->pipestat_irq_mask[pipe];  in i9xx_pipestat_irq_ack()
1475 		pipe_stats[pipe] = intel_uncore_read(&dev_priv->uncore, reg) & status_mask;  in i9xx_pipestat_irq_ack()
1476 		enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);  in i9xx_pipestat_irq_ack()
1488 			intel_uncore_write(&dev_priv->uncore, reg, pipe_stats[pipe]);  in i9xx_pipestat_irq_ack()
1489 			intel_uncore_write(&dev_priv->uncore, reg, enable_mask);  in i9xx_pipestat_irq_ack()
1492 	spin_unlock(&dev_priv->irq_lock);  in i9xx_pipestat_irq_ack()
1495 static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,  in i8xx_pipestat_irq_handler()  argument
1500 	for_each_pipe(dev_priv, pipe) {  in i8xx_pipestat_irq_handler()
1502 			intel_handle_vblank(dev_priv, pipe);  in i8xx_pipestat_irq_handler()
1505 			i9xx_pipe_crc_irq_handler(dev_priv, pipe);  in i8xx_pipestat_irq_handler()
1508 			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);  in i8xx_pipestat_irq_handler()
1512 static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,  in i915_pipestat_irq_handler()  argument
1518 	for_each_pipe(dev_priv, pipe) {  in i915_pipestat_irq_handler()
1520 			intel_handle_vblank(dev_priv, pipe);  in i915_pipestat_irq_handler()
1526 			i9xx_pipe_crc_irq_handler(dev_priv, pipe);  in i915_pipestat_irq_handler()
1529 			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);  in i915_pipestat_irq_handler()
1533 		intel_opregion_asle_intr(dev_priv);  in i915_pipestat_irq_handler()
1536 static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,  in i965_pipestat_irq_handler()  argument
1542 	for_each_pipe(dev_priv, pipe) {  in i965_pipestat_irq_handler()
1544 			intel_handle_vblank(dev_priv, pipe);  in i965_pipestat_irq_handler()
1550 			i9xx_pipe_crc_irq_handler(dev_priv, pipe);  in i965_pipestat_irq_handler()
1553 			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);  in i965_pipestat_irq_handler()
1557 		intel_opregion_asle_intr(dev_priv);  in i965_pipestat_irq_handler()
1560 		gmbus_irq_handler(dev_priv);  in i965_pipestat_irq_handler()
1563 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,  in valleyview_pipestat_irq_handler()  argument
1568 	for_each_pipe(dev_priv, pipe) {  in valleyview_pipestat_irq_handler()
1570 			intel_handle_vblank(dev_priv, pipe);  in valleyview_pipestat_irq_handler()
1573 			flip_done_handler(dev_priv, pipe);  in valleyview_pipestat_irq_handler()
1576 			i9xx_pipe_crc_irq_handler(dev_priv, pipe);  in valleyview_pipestat_irq_handler()
1579 			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);  in valleyview_pipestat_irq_handler()
1583 		gmbus_irq_handler(dev_priv);  in valleyview_pipestat_irq_handler()
1586 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)  in i9xx_hpd_irq_ack()  argument
1591 	if (IS_G4X(dev_priv) ||  in i9xx_hpd_irq_ack()
1592 	    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in i9xx_hpd_irq_ack()
1608 		u32 tmp = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT) & hotplug_status_mask;  in i9xx_hpd_irq_ack()
1614 		intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, hotplug_status);  in i9xx_hpd_irq_ack()
1617 	drm_WARN_ONCE(&dev_priv->drm, 1,  in i9xx_hpd_irq_ack()
1619 		      intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));  in i9xx_hpd_irq_ack()
1624 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,  in i9xx_hpd_irq_handler()  argument
1630 	if (IS_G4X(dev_priv) ||  in i9xx_hpd_irq_handler()
1631 	    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in i9xx_hpd_irq_handler()
1637 		intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,  in i9xx_hpd_irq_handler()
1639 				   dev_priv->hotplug.hpd,  in i9xx_hpd_irq_handler()
1642 		intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);  in i9xx_hpd_irq_handler()
1645 	if ((IS_G4X(dev_priv) ||  in i9xx_hpd_irq_handler()
1646 	     IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&  in i9xx_hpd_irq_handler()
1648 		dp_aux_irq_handler(dev_priv);  in i9xx_hpd_irq_handler()
1653 	struct drm_i915_private *dev_priv = arg;  in valleyview_irq_handler()  local
1656 	if (!intel_irqs_enabled(dev_priv))  in valleyview_irq_handler()
1660 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);  in valleyview_irq_handler()
1668 		gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR);  in valleyview_irq_handler()
1669 		pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR);  in valleyview_irq_handler()
1670 		iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);  in valleyview_irq_handler()
1690 		intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0);  in valleyview_irq_handler()
1691 		ier = intel_uncore_read(&dev_priv->uncore, VLV_IER);  in valleyview_irq_handler()
1692 		intel_uncore_write(&dev_priv->uncore, VLV_IER, 0);  in valleyview_irq_handler()
1695 			intel_uncore_write(&dev_priv->uncore, GTIIR, gt_iir);  in valleyview_irq_handler()
1697 			intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir);  in valleyview_irq_handler()
1700 			hotplug_status = i9xx_hpd_irq_ack(dev_priv);  in valleyview_irq_handler()
1704 		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);  in valleyview_irq_handler()
1708 			intel_lpe_audio_irq_handler(dev_priv);  in valleyview_irq_handler()
1715 			intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);  in valleyview_irq_handler()
1717 		intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);  in valleyview_irq_handler()
1718 		intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);  in valleyview_irq_handler()
1721 			gen6_gt_irq_handler(&dev_priv->gt, gt_iir);  in valleyview_irq_handler()
1723 			gen6_rps_irq_handler(&dev_priv->gt.rps, pm_iir);  in valleyview_irq_handler()
1726 			i9xx_hpd_irq_handler(dev_priv, hotplug_status);  in valleyview_irq_handler()
1728 		valleyview_pipestat_irq_handler(dev_priv, pipe_stats);  in valleyview_irq_handler()
1731 	pmu_irq_stats(dev_priv, ret);  in valleyview_irq_handler()
1733 	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);  in valleyview_irq_handler()
1740 	struct drm_i915_private *dev_priv = arg;  in cherryview_irq_handler()  local
1743 	if (!intel_irqs_enabled(dev_priv))  in cherryview_irq_handler()
1747 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);  in cherryview_irq_handler()
1755 		master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;  in cherryview_irq_handler()
1756 		iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);  in cherryview_irq_handler()
1776 		intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0);  in cherryview_irq_handler()
1777 		ier = intel_uncore_read(&dev_priv->uncore, VLV_IER);  in cherryview_irq_handler()
1778 		intel_uncore_write(&dev_priv->uncore, VLV_IER, 0);  in cherryview_irq_handler()
1780 		gen8_gt_irq_handler(&dev_priv->gt, master_ctl);  in cherryview_irq_handler()
1783 			hotplug_status = i9xx_hpd_irq_ack(dev_priv);  in cherryview_irq_handler()
1787 		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);  in cherryview_irq_handler()
1792 			intel_lpe_audio_irq_handler(dev_priv);  in cherryview_irq_handler()
1799 			intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);  in cherryview_irq_handler()
1801 		intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);  in cherryview_irq_handler()
1802 		intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);  in cherryview_irq_handler()
1805 			i9xx_hpd_irq_handler(dev_priv, hotplug_status);  in cherryview_irq_handler()
1807 		valleyview_pipestat_irq_handler(dev_priv, pipe_stats);  in cherryview_irq_handler()
1810 	pmu_irq_stats(dev_priv, ret);  in cherryview_irq_handler()
1812 	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);  in cherryview_irq_handler()
1817 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,  in ibx_hpd_irq_handler()  argument
1828 	dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);  in ibx_hpd_irq_handler()
1837 	intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg);  in ibx_hpd_irq_handler()
1841 	intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,  in ibx_hpd_irq_handler()
1843 			   dev_priv->hotplug.pch_hpd,  in ibx_hpd_irq_handler()
1846 	intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);  in ibx_hpd_irq_handler()
1849 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)  in ibx_irq_handler()  argument
1854 	ibx_hpd_irq_handler(dev_priv, hotplug_trigger);  in ibx_irq_handler()
1859 		drm_dbg(&dev_priv->drm, "PCH audio power change on port %d\n",  in ibx_irq_handler()
1864 		dp_aux_irq_handler(dev_priv);  in ibx_irq_handler()
1867 		gmbus_irq_handler(dev_priv);  in ibx_irq_handler()
1870 		drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n");  in ibx_irq_handler()
1873 		drm_dbg(&dev_priv->drm, "PCH transcoder audio interrupt\n");  in ibx_irq_handler()
1876 		drm_err(&dev_priv->drm, "PCH poison interrupt\n");  in ibx_irq_handler()
1879 		for_each_pipe(dev_priv, pipe)  in ibx_irq_handler()
1880 			drm_dbg(&dev_priv->drm, "  pipe %c FDI IIR: 0x%08x\n",  in ibx_irq_handler()
1882 				intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe)));  in ibx_irq_handler()
1886 		drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n");  in ibx_irq_handler()
1889 		drm_dbg(&dev_priv->drm,  in ibx_irq_handler()
1893 		intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);  in ibx_irq_handler()
1896 		intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);  in ibx_irq_handler()
1899 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)  in ivb_err_int_handler()  argument
1901 	u32 err_int = intel_uncore_read(&dev_priv->uncore, GEN7_ERR_INT);  in ivb_err_int_handler()
1905 		drm_err(&dev_priv->drm, "Poison interrupt\n");  in ivb_err_int_handler()
1907 	for_each_pipe(dev_priv, pipe) {  in ivb_err_int_handler()
1909 			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);  in ivb_err_int_handler()
1912 			if (IS_IVYBRIDGE(dev_priv))  in ivb_err_int_handler()
1913 				ivb_pipe_crc_irq_handler(dev_priv, pipe);  in ivb_err_int_handler()
1915 				hsw_pipe_crc_irq_handler(dev_priv, pipe);  in ivb_err_int_handler()
1919 	intel_uncore_write(&dev_priv->uncore, GEN7_ERR_INT, err_int);  in ivb_err_int_handler()
1922 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)  in cpt_serr_int_handler()  argument
1924 	u32 serr_int = intel_uncore_read(&dev_priv->uncore, SERR_INT);  in cpt_serr_int_handler()
1928 		drm_err(&dev_priv->drm, "PCH poison interrupt\n");  in cpt_serr_int_handler()
1930 	for_each_pipe(dev_priv, pipe)  in cpt_serr_int_handler()
1932 			intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);  in cpt_serr_int_handler()
1934 	intel_uncore_write(&dev_priv->uncore, SERR_INT, serr_int);  in cpt_serr_int_handler()
1937 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)  in cpt_irq_handler()  argument
1942 	ibx_hpd_irq_handler(dev_priv, hotplug_trigger);  in cpt_irq_handler()
1947 		drm_dbg(&dev_priv->drm, "PCH audio power change on port %c\n",  in cpt_irq_handler()
1952 		dp_aux_irq_handler(dev_priv);  in cpt_irq_handler()
1955 		gmbus_irq_handler(dev_priv);  in cpt_irq_handler()
1958 		drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n");  in cpt_irq_handler()
1961 		drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n");  in cpt_irq_handler()
1964 		for_each_pipe(dev_priv, pipe)  in cpt_irq_handler()
1965 			drm_dbg(&dev_priv->drm, "  pipe %c FDI IIR: 0x%08x\n",  in cpt_irq_handler()
1967 				intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe)));  in cpt_irq_handler()
1971 		cpt_serr_int_handler(dev_priv);  in cpt_irq_handler()
1974 static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)  in icp_irq_handler()  argument
1983 		dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_DDI);  in icp_irq_handler()
1984 		intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_DDI, dig_hotplug_reg);  in icp_irq_handler()
1986 		intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,  in icp_irq_handler()
1988 				   dev_priv->hotplug.pch_hpd,  in icp_irq_handler()
1995 		dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_TC);  in icp_irq_handler()
1996 		intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_TC, dig_hotplug_reg);  in icp_irq_handler()
1998 		intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,  in icp_irq_handler()
2000 				   dev_priv->hotplug.pch_hpd,  in icp_irq_handler()
2005 		intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);  in icp_irq_handler()
2008 		gmbus_irq_handler(dev_priv);  in icp_irq_handler()
2011 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)  in spt_irq_handler()  argument
2021 		dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);  in spt_irq_handler()
2022 		intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg);  in spt_irq_handler()
2024 		intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,  in spt_irq_handler()
2026 				   dev_priv->hotplug.pch_hpd,  in spt_irq_handler()
2033 		dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG2);  in spt_irq_handler()
2034 		intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG2, dig_hotplug_reg);  in spt_irq_handler()
2036 		intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,  in spt_irq_handler()
2038 				   dev_priv->hotplug.pch_hpd,  in spt_irq_handler()
2043 		intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);  in spt_irq_handler()
2046 		gmbus_irq_handler(dev_priv);  in spt_irq_handler()
2049 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,  in ilk_hpd_irq_handler()  argument
2054 	dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL);  in ilk_hpd_irq_handler()
2055 	intel_uncore_write(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);  in ilk_hpd_irq_handler()
2057 	intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,  in ilk_hpd_irq_handler()
2059 			   dev_priv->hotplug.hpd,  in ilk_hpd_irq_handler()
2062 	intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);  in ilk_hpd_irq_handler()
2065 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,  in ilk_display_irq_handler()  argument
2072 		ilk_hpd_irq_handler(dev_priv, hotplug_trigger);  in ilk_display_irq_handler()
2075 		dp_aux_irq_handler(dev_priv);  in ilk_display_irq_handler()
2078 		intel_opregion_asle_intr(dev_priv);  in ilk_display_irq_handler()
2081 		drm_err(&dev_priv->drm, "Poison interrupt\n");  in ilk_display_irq_handler()
2083 	for_each_pipe(dev_priv, pipe) {  in ilk_display_irq_handler()
2085 			intel_handle_vblank(dev_priv, pipe);  in ilk_display_irq_handler()
2088 			flip_done_handler(dev_priv, pipe);  in ilk_display_irq_handler()
2091 			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);  in ilk_display_irq_handler()
2094 			i9xx_pipe_crc_irq_handler(dev_priv, pipe);  in ilk_display_irq_handler()
2099 		u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR);  in ilk_display_irq_handler()
2101 		if (HAS_PCH_CPT(dev_priv))  in ilk_display_irq_handler()
2102 			cpt_irq_handler(dev_priv, pch_iir);  in ilk_display_irq_handler()
2104 			ibx_irq_handler(dev_priv, pch_iir);  in ilk_display_irq_handler()
2107 		intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir);  in ilk_display_irq_handler()
2110 	if (DISPLAY_VER(dev_priv) == 5 && de_iir & DE_PCU_EVENT)  in ilk_display_irq_handler()
2111 		gen5_rps_irq_handler(&dev_priv->gt.rps);  in ilk_display_irq_handler()
2114 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,  in ivb_display_irq_handler()  argument
2121 		ilk_hpd_irq_handler(dev_priv, hotplug_trigger);  in ivb_display_irq_handler()
2124 		ivb_err_int_handler(dev_priv);  in ivb_display_irq_handler()
2127 		dp_aux_irq_handler(dev_priv);  in ivb_display_irq_handler()
2130 		intel_opregion_asle_intr(dev_priv);  in ivb_display_irq_handler()
2132 	for_each_pipe(dev_priv, pipe) {  in ivb_display_irq_handler()
2134 			intel_handle_vblank(dev_priv, pipe);  in ivb_display_irq_handler()
2137 			flip_done_handler(dev_priv, pipe);  in ivb_display_irq_handler()
2141 	if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {  in ivb_display_irq_handler()
2142 		u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR);  in ivb_display_irq_handler()
2144 		cpt_irq_handler(dev_priv, pch_iir);  in ivb_display_irq_handler()
2147 		intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir);  in ivb_display_irq_handler()
2229 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,  in bxt_hpd_irq_handler()  argument
2234 	dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);  in bxt_hpd_irq_handler()
2235 	intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg);  in bxt_hpd_irq_handler()
2237 	intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,  in bxt_hpd_irq_handler()
2239 			   dev_priv->hotplug.hpd,  in bxt_hpd_irq_handler()
2242 	intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);  in bxt_hpd_irq_handler()
2245 static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)  in gen11_hpd_irq_handler()  argument
2254 		dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL);  in gen11_hpd_irq_handler()
2255 		intel_uncore_write(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);  in gen11_hpd_irq_handler()
2257 		intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,  in gen11_hpd_irq_handler()
2259 				   dev_priv->hotplug.hpd,  in gen11_hpd_irq_handler()
2266 		dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL);  in gen11_hpd_irq_handler()
2267 		intel_uncore_write(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);  in gen11_hpd_irq_handler()
2269 		intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,  in gen11_hpd_irq_handler()
2271 				   dev_priv->hotplug.hpd,  in gen11_hpd_irq_handler()
2276 		intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);  in gen11_hpd_irq_handler()
2278 		drm_err(&dev_priv->drm,  in gen11_hpd_irq_handler()
2282 static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)  in gen8_de_port_aux_mask()  argument
2286 	if (DISPLAY_VER(dev_priv) >= 13)  in gen8_de_port_aux_mask()
2296 	else if (DISPLAY_VER(dev_priv) >= 12)  in gen8_de_port_aux_mask()
2309 	if (DISPLAY_VER(dev_priv) >= 9)  in gen8_de_port_aux_mask()
2314 	if (DISPLAY_VER(dev_priv) == 11) {  in gen8_de_port_aux_mask()
2322 static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)  in gen8_de_pipe_fault_mask()  argument
2324 	if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))  in gen8_de_pipe_fault_mask()
2326 	else if (DISPLAY_VER(dev_priv) >= 11)  in gen8_de_pipe_fault_mask()
2328 	else if (DISPLAY_VER(dev_priv) >= 9)  in gen8_de_pipe_fault_mask()
2335 gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)  in gen8_de_misc_irq_handler()  argument
2340 		intel_opregion_asle_intr(dev_priv);  in gen8_de_misc_irq_handler()
2349 		for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {  in gen8_de_misc_irq_handler()
2352 			if (DISPLAY_VER(dev_priv) >= 12)  in gen8_de_misc_irq_handler()
2357 			psr_iir = intel_uncore_read(&dev_priv->uncore, iir_reg);  in gen8_de_misc_irq_handler()
2358 			intel_uncore_write(&dev_priv->uncore, iir_reg, psr_iir);  in gen8_de_misc_irq_handler()
2366 			if (DISPLAY_VER(dev_priv) < 12)  in gen8_de_misc_irq_handler()
2372 		drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n");  in gen8_de_misc_irq_handler()
2375 static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,  in gen11_dsi_te_interrupt_handler()  argument
2387 	val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));  in gen11_dsi_te_interrupt_handler()
2399 	val = intel_uncore_read(&dev_priv->uncore, DSI_TRANS_FUNC_CONF(dsi_trans));  in gen11_dsi_te_interrupt_handler()
2403 		drm_err(&dev_priv->drm, "DSI trancoder not configured in command mode\n");  in gen11_dsi_te_interrupt_handler()
2408 	val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL(dsi_trans));  in gen11_dsi_te_interrupt_handler()
2420 		drm_err(&dev_priv->drm, "Invalid PIPE\n");  in gen11_dsi_te_interrupt_handler()
2424 	intel_handle_vblank(dev_priv, pipe);  in gen11_dsi_te_interrupt_handler()
2428 	tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_IDENT_REG(port));  in gen11_dsi_te_interrupt_handler()
2429 	intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp);  in gen11_dsi_te_interrupt_handler()
2440 u32 gen8_de_pipe_underrun_mask(struct drm_i915_private *dev_priv)  in gen8_de_pipe_underrun_mask()  argument
2444 	if (DISPLAY_VER(dev_priv) >= 13)  in gen8_de_pipe_underrun_mask()
2452 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)  in gen8_de_irq_handler()  argument
2458 	drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv));  in gen8_de_irq_handler()
2461 		iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IIR);  in gen8_de_irq_handler()
2463 			intel_uncore_write(&dev_priv->uncore, GEN8_DE_MISC_IIR, iir);  in gen8_de_irq_handler()
2465 			gen8_de_misc_irq_handler(dev_priv, iir);  in gen8_de_irq_handler()
2467 			drm_err(&dev_priv->drm,  in gen8_de_irq_handler()
2472 	if (DISPLAY_VER(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {  in gen8_de_irq_handler()
2473 		iir = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IIR);  in gen8_de_irq_handler()
2475 			intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IIR, iir);  in gen8_de_irq_handler()
2477 			gen11_hpd_irq_handler(dev_priv, iir);  in gen8_de_irq_handler()
2479 			drm_err(&dev_priv->drm,  in gen8_de_irq_handler()
2485 		iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IIR);  in gen8_de_irq_handler()
2489 			intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IIR, iir);  in gen8_de_irq_handler()
2492 			if (iir & gen8_de_port_aux_mask(dev_priv)) {  in gen8_de_irq_handler()
2493 				dp_aux_irq_handler(dev_priv);  in gen8_de_irq_handler()
2497 			if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {  in gen8_de_irq_handler()
2501 					bxt_hpd_irq_handler(dev_priv, hotplug_trigger);  in gen8_de_irq_handler()
2504 			} else if (IS_BROADWELL(dev_priv)) {  in gen8_de_irq_handler()
2508 					ilk_hpd_irq_handler(dev_priv, hotplug_trigger);  in gen8_de_irq_handler()
2513 			if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&  in gen8_de_irq_handler()
2515 				gmbus_irq_handler(dev_priv);  in gen8_de_irq_handler()
2519 			if (DISPLAY_VER(dev_priv) >= 11) {  in gen8_de_irq_handler()
2523 					gen11_dsi_te_interrupt_handler(dev_priv, te_trigger);  in gen8_de_irq_handler()
2529 				drm_err(&dev_priv->drm,  in gen8_de_irq_handler()
2533 			drm_err(&dev_priv->drm,  in gen8_de_irq_handler()
2537 	for_each_pipe(dev_priv, pipe) {  in gen8_de_irq_handler()
2543 		iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe));  in gen8_de_irq_handler()
2545 			drm_err(&dev_priv->drm,  in gen8_de_irq_handler()
2551 		intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir);  in gen8_de_irq_handler()
2554 			intel_handle_vblank(dev_priv, pipe);  in gen8_de_irq_handler()
2556 		if (iir & gen8_de_pipe_flip_done_mask(dev_priv))  in gen8_de_irq_handler()
2557 			flip_done_handler(dev_priv, pipe);  in gen8_de_irq_handler()
2560 			hsw_pipe_crc_irq_handler(dev_priv, pipe);  in gen8_de_irq_handler()
2562 		if (iir & gen8_de_pipe_underrun_mask(dev_priv))  in gen8_de_irq_handler()
2563 			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);  in gen8_de_irq_handler()
2565 		fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);  in gen8_de_irq_handler()
2567 			drm_err(&dev_priv->drm,  in gen8_de_irq_handler()
2573 	if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&  in gen8_de_irq_handler()
2580 		iir = intel_uncore_read(&dev_priv->uncore, SDEIIR);  in gen8_de_irq_handler()
2582 			intel_uncore_write(&dev_priv->uncore, SDEIIR, iir);  in gen8_de_irq_handler()
2585 			if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)  in gen8_de_irq_handler()
2586 				icp_irq_handler(dev_priv, iir);  in gen8_de_irq_handler()
2587 			else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)  in gen8_de_irq_handler()
2588 				spt_irq_handler(dev_priv, iir);  in gen8_de_irq_handler()
2590 				cpt_irq_handler(dev_priv, iir);  in gen8_de_irq_handler()
2596 			drm_dbg(&dev_priv->drm,  in gen8_de_irq_handler()
2624 	struct drm_i915_private *dev_priv = arg;  in gen8_irq_handler()  local
2625 	void __iomem * const regs = dev_priv->uncore.regs;  in gen8_irq_handler()
2628 	if (!intel_irqs_enabled(dev_priv))  in gen8_irq_handler()
2638 	gen8_gt_irq_handler(&dev_priv->gt, master_ctl);  in gen8_irq_handler()
2642 		disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);  in gen8_irq_handler()
2643 		gen8_de_irq_handler(dev_priv, master_ctl);  in gen8_irq_handler()
2644 		enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);  in gen8_irq_handler()
2649 	pmu_irq_stats(dev_priv, IRQ_HANDLED);  in gen8_irq_handler()
2819 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);  in i8xx_enable_vblank()  local
2823 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);  in i8xx_enable_vblank()
2824 	i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);  in i8xx_enable_vblank()
2825 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);  in i8xx_enable_vblank()
2832 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);  in i915gm_enable_vblank()  local
2840 	if (dev_priv->vblank_enabled++ == 0)  in i915gm_enable_vblank()
2841 …intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));  in i915gm_enable_vblank()
2848 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);  in i965_enable_vblank()  local
2852 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);  in i965_enable_vblank()
2853 	i915_enable_pipestat(dev_priv, pipe,  in i965_enable_vblank()
2855 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);  in i965_enable_vblank()
2862 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);  in ilk_enable_vblank()  local
2865 	u32 bit = DISPLAY_VER(dev_priv) >= 7 ?  in ilk_enable_vblank()
2868 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);  in ilk_enable_vblank()
2869 	ilk_enable_display_irq(dev_priv, bit);  in ilk_enable_vblank()
2870 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);  in ilk_enable_vblank()
2875 	if (HAS_PSR(dev_priv))  in ilk_enable_vblank()
2884 	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);  in gen11_dsi_configure_te()  local
2898 	tmp =  intel_uncore_read(&dev_priv->uncore, DSI_INTR_MASK_REG(port));  in gen11_dsi_configure_te()
2904 	intel_uncore_write(&dev_priv->uncore, DSI_INTR_MASK_REG(port), tmp);  in gen11_dsi_configure_te()
2906 	tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_IDENT_REG(port));  in gen11_dsi_configure_te()
2907 	intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp);  in gen11_dsi_configure_te()
2915 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in bdw_enable_vblank()  local
2922 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);  in bdw_enable_vblank()
2923 	bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);  in bdw_enable_vblank()
2924 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);  in bdw_enable_vblank()
2929 	if (HAS_PSR(dev_priv))  in bdw_enable_vblank()
2940 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);  in i8xx_disable_vblank()  local
2944 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);  in i8xx_disable_vblank()
2945 	i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);  in i8xx_disable_vblank()
2946 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);  in i8xx_disable_vblank()
2951 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);  in i915gm_disable_vblank()  local
2955 	if (--dev_priv->vblank_enabled == 0)  in i915gm_disable_vblank()
2956 …intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)…  in i915gm_disable_vblank()
2961 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);  in i965_disable_vblank()  local
2965 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);  in i965_disable_vblank()
2966 	i915_disable_pipestat(dev_priv, pipe,  in i965_disable_vblank()
2968 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);  in i965_disable_vblank()
2973 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);  in ilk_disable_vblank()  local
2976 	u32 bit = DISPLAY_VER(dev_priv) >= 7 ?  in ilk_disable_vblank()
2979 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);  in ilk_disable_vblank()
2980 	ilk_disable_display_irq(dev_priv, bit);  in ilk_disable_vblank()
2981 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);  in ilk_disable_vblank()
2987 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in bdw_disable_vblank()  local
2994 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);  in bdw_disable_vblank()
2995 	bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);  in bdw_disable_vblank()
2996 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);  in bdw_disable_vblank()
2999 static void ibx_irq_reset(struct drm_i915_private *dev_priv)  in ibx_irq_reset()  argument
3001 	struct intel_uncore *uncore = &dev_priv->uncore;  in ibx_irq_reset()
3003 	if (HAS_PCH_NOP(dev_priv))  in ibx_irq_reset()
3008 	if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))  in ibx_irq_reset()
3009 		intel_uncore_write(&dev_priv->uncore, SERR_INT, 0xffffffff);  in ibx_irq_reset()
3012 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)  in vlv_display_irq_reset()  argument
3014 	struct intel_uncore *uncore = &dev_priv->uncore;  in vlv_display_irq_reset()
3016 	if (IS_CHERRYVIEW(dev_priv))  in vlv_display_irq_reset()
3021 	i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);  in vlv_display_irq_reset()
3022 …intel_uncore_write(uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_ST…  in vlv_display_irq_reset()
3024 	i9xx_pipestat_irq_reset(dev_priv);  in vlv_display_irq_reset()
3027 	dev_priv->irq_mask = ~0u;  in vlv_display_irq_reset()
3030 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)  in vlv_display_irq_postinstall()  argument
3032 	struct intel_uncore *uncore = &dev_priv->uncore;  in vlv_display_irq_postinstall()
3040 	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);  in vlv_display_irq_postinstall()
3041 	for_each_pipe(dev_priv, pipe)  in vlv_display_irq_postinstall()
3042 		i915_enable_pipestat(dev_priv, pipe, pipestat_mask);  in vlv_display_irq_postinstall()
3050 	if (IS_CHERRYVIEW(dev_priv))  in vlv_display_irq_postinstall()
3054 	drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u);  in vlv_display_irq_postinstall()
3056 	dev_priv->irq_mask = ~enable_mask;  in vlv_display_irq_postinstall()
3058 	GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask);  in vlv_display_irq_postinstall()
3063 static void ilk_irq_reset(struct drm_i915_private *dev_priv)  in ilk_irq_reset()  argument
3065 	struct intel_uncore *uncore = &dev_priv->uncore;  in ilk_irq_reset()
3068 	dev_priv->irq_mask = ~0u;  in ilk_irq_reset()
3070 	if (GRAPHICS_VER(dev_priv) == 7)  in ilk_irq_reset()
3073 	if (IS_HASWELL(dev_priv)) {  in ilk_irq_reset()
3078 	gen5_gt_irq_reset(&dev_priv->gt);  in ilk_irq_reset()
3080 	ibx_irq_reset(dev_priv);  in ilk_irq_reset()
3083 static void valleyview_irq_reset(struct drm_i915_private *dev_priv)  in valleyview_irq_reset()  argument
3085 	intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0);  in valleyview_irq_reset()
3086 	intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);  in valleyview_irq_reset()
3088 	gen5_gt_irq_reset(&dev_priv->gt);  in valleyview_irq_reset()
3090 	spin_lock_irq(&dev_priv->irq_lock);  in valleyview_irq_reset()
3091 	if (dev_priv->display_irqs_enabled)  in valleyview_irq_reset()
3092 		vlv_display_irq_reset(dev_priv);  in valleyview_irq_reset()
3093 	spin_unlock_irq(&dev_priv->irq_lock);  in valleyview_irq_reset()
3096 static void gen8_display_irq_reset(struct drm_i915_private *dev_priv)  in gen8_display_irq_reset()  argument
3098 	struct intel_uncore *uncore = &dev_priv->uncore;  in gen8_display_irq_reset()
3101 	if (!HAS_DISPLAY(dev_priv))  in gen8_display_irq_reset()
3107 	for_each_pipe(dev_priv, pipe)  in gen8_display_irq_reset()
3108 		if (intel_display_power_is_enabled(dev_priv,  in gen8_display_irq_reset()
3116 static void gen8_irq_reset(struct drm_i915_private *dev_priv)  in gen8_irq_reset()  argument
3118 	struct intel_uncore *uncore = &dev_priv->uncore;  in gen8_irq_reset()
3120 	gen8_master_intr_disable(dev_priv->uncore.regs);  in gen8_irq_reset()
3122 	gen8_gt_irq_reset(&dev_priv->gt);  in gen8_irq_reset()
3123 	gen8_display_irq_reset(dev_priv);  in gen8_irq_reset()
3126 	if (HAS_PCH_SPLIT(dev_priv))  in gen8_irq_reset()
3127 		ibx_irq_reset(dev_priv);  in gen8_irq_reset()
3131 static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)  in gen11_display_irq_reset()  argument
3133 	struct intel_uncore *uncore = &dev_priv->uncore;  in gen11_display_irq_reset()
3138 	if (!HAS_DISPLAY(dev_priv))  in gen11_display_irq_reset()
3143 	if (DISPLAY_VER(dev_priv) >= 12) {  in gen11_display_irq_reset()
3146 		for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {  in gen11_display_irq_reset()
3150 			if (!intel_display_power_is_enabled(dev_priv, domain))  in gen11_display_irq_reset()
3161 	for_each_pipe(dev_priv, pipe)  in gen11_display_irq_reset()
3162 		if (intel_display_power_is_enabled(dev_priv,  in gen11_display_irq_reset()
3170 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)  in gen11_display_irq_reset()
3174 static void gen11_irq_reset(struct drm_i915_private *dev_priv)  in gen11_irq_reset()  argument
3176 	struct intel_uncore *uncore = &dev_priv->uncore;  in gen11_irq_reset()
3178 	gen11_master_intr_disable(dev_priv->uncore.regs);  in gen11_irq_reset()
3180 	gen11_gt_irq_reset(&dev_priv->gt);  in gen11_irq_reset()
3181 	gen11_display_irq_reset(dev_priv);  in gen11_irq_reset()
3187 static void dg1_irq_reset(struct drm_i915_private *dev_priv)  in dg1_irq_reset()  argument
3189 	struct intel_uncore *uncore = &dev_priv->uncore;  in dg1_irq_reset()
3191 	dg1_master_intr_disable(dev_priv->uncore.regs);  in dg1_irq_reset()
3193 	gen11_gt_irq_reset(&dev_priv->gt);  in dg1_irq_reset()
3194 	gen11_display_irq_reset(dev_priv);  in dg1_irq_reset()
3200 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,  in gen8_irq_power_well_post_enable()  argument
3203 	struct intel_uncore *uncore = &dev_priv->uncore;  in gen8_irq_power_well_post_enable()
3205 		gen8_de_pipe_underrun_mask(dev_priv) |  in gen8_irq_power_well_post_enable()
3206 		gen8_de_pipe_flip_done_mask(dev_priv);  in gen8_irq_power_well_post_enable()
3209 	spin_lock_irq(&dev_priv->irq_lock);  in gen8_irq_power_well_post_enable()
3211 	if (!intel_irqs_enabled(dev_priv)) {  in gen8_irq_power_well_post_enable()
3212 		spin_unlock_irq(&dev_priv->irq_lock);  in gen8_irq_power_well_post_enable()
3216 	for_each_pipe_masked(dev_priv, pipe, pipe_mask)  in gen8_irq_power_well_post_enable()
3218 				  dev_priv->de_irq_mask[pipe],  in gen8_irq_power_well_post_enable()
3219 				  ~dev_priv->de_irq_mask[pipe] | extra_ier);  in gen8_irq_power_well_post_enable()
3221 	spin_unlock_irq(&dev_priv->irq_lock);  in gen8_irq_power_well_post_enable()
3224 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,  in gen8_irq_power_well_pre_disable()  argument
3227 	struct intel_uncore *uncore = &dev_priv->uncore;  in gen8_irq_power_well_pre_disable()
3230 	spin_lock_irq(&dev_priv->irq_lock);  in gen8_irq_power_well_pre_disable()
3232 	if (!intel_irqs_enabled(dev_priv)) {  in gen8_irq_power_well_pre_disable()
3233 		spin_unlock_irq(&dev_priv->irq_lock);  in gen8_irq_power_well_pre_disable()
3237 	for_each_pipe_masked(dev_priv, pipe, pipe_mask)  in gen8_irq_power_well_pre_disable()
3240 	spin_unlock_irq(&dev_priv->irq_lock);  in gen8_irq_power_well_pre_disable()
3243 	intel_synchronize_irq(dev_priv);  in gen8_irq_power_well_pre_disable()
3246 static void cherryview_irq_reset(struct drm_i915_private *dev_priv)  in cherryview_irq_reset()  argument
3248 	struct intel_uncore *uncore = &dev_priv->uncore;  in cherryview_irq_reset()
3250 	intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0);  in cherryview_irq_reset()
3251 	intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);  in cherryview_irq_reset()
3253 	gen8_gt_irq_reset(&dev_priv->gt);  in cherryview_irq_reset()
3257 	spin_lock_irq(&dev_priv->irq_lock);  in cherryview_irq_reset()
3258 	if (dev_priv->display_irqs_enabled)  in cherryview_irq_reset()
3259 		vlv_display_irq_reset(dev_priv);  in cherryview_irq_reset()
3260 	spin_unlock_irq(&dev_priv->irq_lock);  in cherryview_irq_reset()
3288 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)  in ibx_hpd_detection_setup()  argument
3297 	hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);  in ibx_hpd_detection_setup()
3305 	hotplug |= intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables);  in ibx_hpd_detection_setup()
3306 	intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug);  in ibx_hpd_detection_setup()
3309 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)  in ibx_hpd_irq_setup()  argument
3313 	enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);  in ibx_hpd_irq_setup()
3314 	hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);  in ibx_hpd_irq_setup()
3316 	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);  in ibx_hpd_irq_setup()
3318 	ibx_hpd_detection_setup(dev_priv);  in ibx_hpd_irq_setup()
3351 static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv)  in icp_ddi_hpd_detection_setup()  argument
3355 	hotplug = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_DDI);  in icp_ddi_hpd_detection_setup()
3360 	hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_ddi_hotplug_enables);  in icp_ddi_hpd_detection_setup()
3361 	intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_DDI, hotplug);  in icp_ddi_hpd_detection_setup()
3364 static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)  in icp_tc_hpd_detection_setup()  argument
3368 	hotplug = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_TC);  in icp_tc_hpd_detection_setup()
3375 	hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_tc_hotplug_enables);  in icp_tc_hpd_detection_setup()
3376 	intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_TC, hotplug);  in icp_tc_hpd_detection_setup()
3379 static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)  in icp_hpd_irq_setup()  argument
3383 	enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);  in icp_hpd_irq_setup()
3384 	hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);  in icp_hpd_irq_setup()
3386 	if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP)  in icp_hpd_irq_setup()
3387 		intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);  in icp_hpd_irq_setup()
3389 	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);  in icp_hpd_irq_setup()
3391 	icp_ddi_hpd_detection_setup(dev_priv);  in icp_hpd_irq_setup()
3392 	icp_tc_hpd_detection_setup(dev_priv);  in icp_hpd_irq_setup()
3411 static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)  in dg1_hpd_irq_setup()  argument
3415 	val = intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN1);  in dg1_hpd_irq_setup()
3420 	intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN1, val);  in dg1_hpd_irq_setup()
3422 	icp_hpd_irq_setup(dev_priv);  in dg1_hpd_irq_setup()
3425 static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)  in gen11_tc_hpd_detection_setup()  argument
3429 	hotplug = intel_uncore_read(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL);  in gen11_tc_hpd_detection_setup()
3436 	hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables);  in gen11_tc_hpd_detection_setup()
3437 	intel_uncore_write(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, hotplug);  in gen11_tc_hpd_detection_setup()
3440 static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)  in gen11_tbt_hpd_detection_setup()  argument
3444 	hotplug = intel_uncore_read(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL);  in gen11_tbt_hpd_detection_setup()
3451 	hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables);  in gen11_tbt_hpd_detection_setup()
3452 	intel_uncore_write(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, hotplug);  in gen11_tbt_hpd_detection_setup()
3455 static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)  in gen11_hpd_irq_setup()  argument
3460 	enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);  in gen11_hpd_irq_setup()
3461 	hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);  in gen11_hpd_irq_setup()
3463 	val = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IMR);  in gen11_hpd_irq_setup()
3466 	intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IMR, val);  in gen11_hpd_irq_setup()
3467 	intel_uncore_posting_read(&dev_priv->uncore, GEN11_DE_HPD_IMR);  in gen11_hpd_irq_setup()
3469 	gen11_tc_hpd_detection_setup(dev_priv);  in gen11_hpd_irq_setup()
3470 	gen11_tbt_hpd_detection_setup(dev_priv);  in gen11_hpd_irq_setup()
3472 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)  in gen11_hpd_irq_setup()
3473 		icp_hpd_irq_setup(dev_priv);  in gen11_hpd_irq_setup()
3504 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)  in spt_hpd_detection_setup()  argument
3509 	if (HAS_PCH_CNP(dev_priv)) {  in spt_hpd_detection_setup()
3510 		val = intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN1);  in spt_hpd_detection_setup()
3513 		intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN1, val);  in spt_hpd_detection_setup()
3517 	hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);  in spt_hpd_detection_setup()
3522 	hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables);  in spt_hpd_detection_setup()
3523 	intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug);  in spt_hpd_detection_setup()
3525 	hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG2);  in spt_hpd_detection_setup()
3527 	hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables);  in spt_hpd_detection_setup()
3528 	intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG2, hotplug);  in spt_hpd_detection_setup()
3531 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)  in spt_hpd_irq_setup()  argument
3535 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)  in spt_hpd_irq_setup()
3536 		intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);  in spt_hpd_irq_setup()
3538 	enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);  in spt_hpd_irq_setup()
3539 	hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);  in spt_hpd_irq_setup()
3541 	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);  in spt_hpd_irq_setup()
3543 	spt_hpd_detection_setup(dev_priv);  in spt_hpd_irq_setup()
3558 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)  in ilk_hpd_detection_setup()  argument
3567 	hotplug = intel_uncore_read(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL);  in ilk_hpd_detection_setup()
3570 	hotplug |= intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables);  in ilk_hpd_detection_setup()
3571 	intel_uncore_write(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);  in ilk_hpd_detection_setup()
3574 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)  in ilk_hpd_irq_setup()  argument
3578 	enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);  in ilk_hpd_irq_setup()
3579 	hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);  in ilk_hpd_irq_setup()
3581 	if (DISPLAY_VER(dev_priv) >= 8)  in ilk_hpd_irq_setup()
3582 		bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);  in ilk_hpd_irq_setup()
3584 		ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);  in ilk_hpd_irq_setup()
3586 	ilk_hpd_detection_setup(dev_priv);  in ilk_hpd_irq_setup()
3588 	ibx_hpd_irq_setup(dev_priv);  in ilk_hpd_irq_setup()
3617 static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)  in bxt_hpd_detection_setup()  argument
3621 	hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);  in bxt_hpd_detection_setup()
3628 	hotplug |= intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables);  in bxt_hpd_detection_setup()
3629 	intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug);  in bxt_hpd_detection_setup()
3632 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)  in bxt_hpd_irq_setup()  argument
3636 	enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);  in bxt_hpd_irq_setup()
3637 	hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);  in bxt_hpd_irq_setup()
3639 	bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);  in bxt_hpd_irq_setup()
3641 	bxt_hpd_detection_setup(dev_priv);  in bxt_hpd_irq_setup()
3655 static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)  in ibx_irq_postinstall()  argument
3657 	struct intel_uncore *uncore = &dev_priv->uncore;  in ibx_irq_postinstall()
3660 	if (HAS_PCH_NOP(dev_priv))  in ibx_irq_postinstall()
3663 	if (HAS_PCH_IBX(dev_priv))  in ibx_irq_postinstall()
3665 	else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))  in ibx_irq_postinstall()
3673 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)  in ilk_irq_postinstall()  argument
3675 	struct intel_uncore *uncore = &dev_priv->uncore;  in ilk_irq_postinstall()
3678 	if (GRAPHICS_VER(dev_priv) >= 7) {  in ilk_irq_postinstall()
3698 	if (IS_HASWELL(dev_priv)) {  in ilk_irq_postinstall()
3703 	if (IS_IRONLAKE_M(dev_priv))  in ilk_irq_postinstall()
3706 	dev_priv->irq_mask = ~display_mask;  in ilk_irq_postinstall()
3708 	ibx_irq_postinstall(dev_priv);  in ilk_irq_postinstall()
3710 	gen5_gt_irq_postinstall(&dev_priv->gt);  in ilk_irq_postinstall()
3712 	GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,  in ilk_irq_postinstall()
3716 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)  in valleyview_enable_display_irqs()  argument
3718 	lockdep_assert_held(&dev_priv->irq_lock);  in valleyview_enable_display_irqs()
3720 	if (dev_priv->display_irqs_enabled)  in valleyview_enable_display_irqs()
3723 	dev_priv->display_irqs_enabled = true;  in valleyview_enable_display_irqs()
3725 	if (intel_irqs_enabled(dev_priv)) {  in valleyview_enable_display_irqs()
3726 		vlv_display_irq_reset(dev_priv);  in valleyview_enable_display_irqs()
3727 		vlv_display_irq_postinstall(dev_priv);  in valleyview_enable_display_irqs()
3731 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)  in valleyview_disable_display_irqs()  argument
3733 	lockdep_assert_held(&dev_priv->irq_lock);  in valleyview_disable_display_irqs()
3735 	if (!dev_priv->display_irqs_enabled)  in valleyview_disable_display_irqs()
3738 	dev_priv->display_irqs_enabled = false;  in valleyview_disable_display_irqs()
3740 	if (intel_irqs_enabled(dev_priv))  in valleyview_disable_display_irqs()
3741 		vlv_display_irq_reset(dev_priv);  in valleyview_disable_display_irqs()
3745 static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)  in valleyview_irq_postinstall()  argument
3747 	gen5_gt_irq_postinstall(&dev_priv->gt);  in valleyview_irq_postinstall()
3749 	spin_lock_irq(&dev_priv->irq_lock);  in valleyview_irq_postinstall()
3750 	if (dev_priv->display_irqs_enabled)  in valleyview_irq_postinstall()
3751 		vlv_display_irq_postinstall(dev_priv);  in valleyview_irq_postinstall()
3752 	spin_unlock_irq(&dev_priv->irq_lock);  in valleyview_irq_postinstall()
3754 	intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);  in valleyview_irq_postinstall()
3755 	intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);  in valleyview_irq_postinstall()
3758 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)  in gen8_de_irq_postinstall()  argument
3760 	struct intel_uncore *uncore = &dev_priv->uncore;  in gen8_de_irq_postinstall()
3762 	u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) |  in gen8_de_irq_postinstall()
3765 	u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);  in gen8_de_irq_postinstall()
3772 	if (!HAS_DISPLAY(dev_priv))  in gen8_de_irq_postinstall()
3775 	if (DISPLAY_VER(dev_priv) <= 10)  in gen8_de_irq_postinstall()
3778 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))  in gen8_de_irq_postinstall()
3781 	if (DISPLAY_VER(dev_priv) >= 11) {  in gen8_de_irq_postinstall()
3784 		if (intel_bios_is_dsi_present(dev_priv, &port))  in gen8_de_irq_postinstall()
3790 		gen8_de_pipe_underrun_mask(dev_priv) |  in gen8_de_irq_postinstall()
3791 		gen8_de_pipe_flip_done_mask(dev_priv);  in gen8_de_irq_postinstall()
3794 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))  in gen8_de_irq_postinstall()
3796 	else if (IS_BROADWELL(dev_priv))  in gen8_de_irq_postinstall()
3799 	if (DISPLAY_VER(dev_priv) >= 12) {  in gen8_de_irq_postinstall()
3802 		for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {  in gen8_de_irq_postinstall()
3806 			if (!intel_display_power_is_enabled(dev_priv, domain))  in gen8_de_irq_postinstall()
3815 	for_each_pipe(dev_priv, pipe) {  in gen8_de_irq_postinstall()
3816 		dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;  in gen8_de_irq_postinstall()
3818 		if (intel_display_power_is_enabled(dev_priv,  in gen8_de_irq_postinstall()
3821 					  dev_priv->de_irq_mask[pipe],  in gen8_de_irq_postinstall()
3828 	if (DISPLAY_VER(dev_priv) >= 11) {  in gen8_de_irq_postinstall()
3838 static void icp_irq_postinstall(struct drm_i915_private *dev_priv)  in icp_irq_postinstall()  argument
3840 	struct intel_uncore *uncore = &dev_priv->uncore;  in icp_irq_postinstall()
3846 static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)  in gen8_irq_postinstall()  argument
3848 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)  in gen8_irq_postinstall()
3849 		icp_irq_postinstall(dev_priv);  in gen8_irq_postinstall()
3850 	else if (HAS_PCH_SPLIT(dev_priv))  in gen8_irq_postinstall()
3851 		ibx_irq_postinstall(dev_priv);  in gen8_irq_postinstall()
3853 	gen8_gt_irq_postinstall(&dev_priv->gt);  in gen8_irq_postinstall()
3854 	gen8_de_irq_postinstall(dev_priv);  in gen8_irq_postinstall()
3856 	gen8_master_intr_enable(dev_priv->uncore.regs);  in gen8_irq_postinstall()
3859 static void gen11_de_irq_postinstall(struct drm_i915_private *dev_priv)  in gen11_de_irq_postinstall()  argument
3861 	if (!HAS_DISPLAY(dev_priv))  in gen11_de_irq_postinstall()
3864 	gen8_de_irq_postinstall(dev_priv);  in gen11_de_irq_postinstall()
3866 	intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL,  in gen11_de_irq_postinstall()
3870 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)  in gen11_irq_postinstall()  argument
3872 	struct intel_uncore *uncore = &dev_priv->uncore;  in gen11_irq_postinstall()
3875 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)  in gen11_irq_postinstall()
3876 		icp_irq_postinstall(dev_priv);  in gen11_irq_postinstall()
3878 	gen11_gt_irq_postinstall(&dev_priv->gt);  in gen11_irq_postinstall()
3879 	gen11_de_irq_postinstall(dev_priv);  in gen11_irq_postinstall()
3884 	intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ);  in gen11_irq_postinstall()
3887 static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)  in dg1_irq_postinstall()  argument
3889 	struct intel_uncore *uncore = &dev_priv->uncore;  in dg1_irq_postinstall()
3892 	gen11_gt_irq_postinstall(&dev_priv->gt);  in dg1_irq_postinstall()
3896 	if (HAS_DISPLAY(dev_priv)) {  in dg1_irq_postinstall()
3897 		icp_irq_postinstall(dev_priv);  in dg1_irq_postinstall()
3898 		gen8_de_irq_postinstall(dev_priv);  in dg1_irq_postinstall()
3899 		intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL,  in dg1_irq_postinstall()
3903 	dg1_master_intr_enable(dev_priv->uncore.regs);  in dg1_irq_postinstall()
3904 	intel_uncore_posting_read(&dev_priv->uncore, DG1_MSTR_TILE_INTR);  in dg1_irq_postinstall()
3907 static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)  in cherryview_irq_postinstall()  argument
3909 	gen8_gt_irq_postinstall(&dev_priv->gt);  in cherryview_irq_postinstall()
3911 	spin_lock_irq(&dev_priv->irq_lock);  in cherryview_irq_postinstall()
3912 	if (dev_priv->display_irqs_enabled)  in cherryview_irq_postinstall()
3913 		vlv_display_irq_postinstall(dev_priv);  in cherryview_irq_postinstall()
3914 	spin_unlock_irq(&dev_priv->irq_lock);  in cherryview_irq_postinstall()
3916 	intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);  in cherryview_irq_postinstall()
3917 	intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);  in cherryview_irq_postinstall()
3920 static void i8xx_irq_reset(struct drm_i915_private *dev_priv)  in i8xx_irq_reset()  argument
3922 	struct intel_uncore *uncore = &dev_priv->uncore;  in i8xx_irq_reset()
3924 	i9xx_pipestat_irq_reset(dev_priv);  in i8xx_irq_reset()
3927 	dev_priv->irq_mask = ~0u;  in i8xx_irq_reset()
3930 static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)  in i8xx_irq_postinstall()  argument
3932 	struct intel_uncore *uncore = &dev_priv->uncore;  in i8xx_irq_postinstall()
3941 	dev_priv->irq_mask =  in i8xx_irq_postinstall()
3952 	GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask);  in i8xx_irq_postinstall()
3956 	spin_lock_irq(&dev_priv->irq_lock);  in i8xx_irq_postinstall()
3957 	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);  in i8xx_irq_postinstall()
3958 	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);  in i8xx_irq_postinstall()
3959 	spin_unlock_irq(&dev_priv->irq_lock);  in i8xx_irq_postinstall()
3992 static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv,  in i8xx_error_irq_handler()  argument
3998 		drm_dbg(&dev_priv->drm, "EIR stuck: 0x%04x, masked\n",  in i8xx_error_irq_handler()
4002 static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,  in i9xx_error_irq_ack()  argument
4007 	*eir = intel_uncore_read(&dev_priv->uncore, EIR);  in i9xx_error_irq_ack()
4009 	intel_uncore_write(&dev_priv->uncore, EIR, *eir);  in i9xx_error_irq_ack()
4011 	*eir_stuck = intel_uncore_read(&dev_priv->uncore, EIR);  in i9xx_error_irq_ack()
4025 	emr = intel_uncore_read(&dev_priv->uncore, EMR);  in i9xx_error_irq_ack()
4026 	intel_uncore_write(&dev_priv->uncore, EMR, 0xffffffff);  in i9xx_error_irq_ack()
4027 	intel_uncore_write(&dev_priv->uncore, EMR, emr | *eir_stuck);  in i9xx_error_irq_ack()
4030 static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv,  in i9xx_error_irq_handler()  argument
4036 		drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n",  in i9xx_error_irq_handler()
4042 	struct drm_i915_private *dev_priv = arg;  in i8xx_irq_handler()  local
4045 	if (!intel_irqs_enabled(dev_priv))  in i8xx_irq_handler()
4049 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);  in i8xx_irq_handler()
4056 		iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR);  in i8xx_irq_handler()
4064 		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);  in i8xx_irq_handler()
4067 			i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck);  in i8xx_irq_handler()
4069 		intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);  in i8xx_irq_handler()
4072 			intel_engine_cs_irq(dev_priv->gt.engine[RCS0], iir);  in i8xx_irq_handler()
4075 			i8xx_error_irq_handler(dev_priv, eir, eir_stuck);  in i8xx_irq_handler()
4077 		i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);  in i8xx_irq_handler()
4080 	pmu_irq_stats(dev_priv, ret);  in i8xx_irq_handler()
4082 	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);  in i8xx_irq_handler()
4087 static void i915_irq_reset(struct drm_i915_private *dev_priv)  in i915_irq_reset()  argument
4089 	struct intel_uncore *uncore = &dev_priv->uncore;  in i915_irq_reset()
4091 	if (I915_HAS_HOTPLUG(dev_priv)) {  in i915_irq_reset()
4092 		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);  in i915_irq_reset()
4093 …intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT…  in i915_irq_reset()
4096 	i9xx_pipestat_irq_reset(dev_priv);  in i915_irq_reset()
4099 	dev_priv->irq_mask = ~0u;  in i915_irq_reset()
4102 static void i915_irq_postinstall(struct drm_i915_private *dev_priv)  in i915_irq_postinstall()  argument
4104 	struct intel_uncore *uncore = &dev_priv->uncore;  in i915_irq_postinstall()
4107 	intel_uncore_write(&dev_priv->uncore, EMR, ~(I915_ERROR_PAGE_TABLE |  in i915_irq_postinstall()
4111 	dev_priv->irq_mask =  in i915_irq_postinstall()
4124 	if (I915_HAS_HOTPLUG(dev_priv)) {  in i915_irq_postinstall()
4128 		dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;  in i915_irq_postinstall()
4131 	GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);  in i915_irq_postinstall()
4135 	spin_lock_irq(&dev_priv->irq_lock);  in i915_irq_postinstall()
4136 	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);  in i915_irq_postinstall()
4137 	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);  in i915_irq_postinstall()
4138 	spin_unlock_irq(&dev_priv->irq_lock);  in i915_irq_postinstall()
4140 	i915_enable_asle_pipestat(dev_priv);  in i915_irq_postinstall()
4145 	struct drm_i915_private *dev_priv = arg;  in i915_irq_handler()  local
4148 	if (!intel_irqs_enabled(dev_priv))  in i915_irq_handler()
4152 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);  in i915_irq_handler()
4160 		iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);  in i915_irq_handler()
4166 		if (I915_HAS_HOTPLUG(dev_priv) &&  in i915_irq_handler()
4168 			hotplug_status = i9xx_hpd_irq_ack(dev_priv);  in i915_irq_handler()
4172 		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);  in i915_irq_handler()
4175 			i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);  in i915_irq_handler()
4177 		intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);  in i915_irq_handler()
4180 			intel_engine_cs_irq(dev_priv->gt.engine[RCS0], iir);  in i915_irq_handler()
4183 			i9xx_error_irq_handler(dev_priv, eir, eir_stuck);  in i915_irq_handler()
4186 			i9xx_hpd_irq_handler(dev_priv, hotplug_status);  in i915_irq_handler()
4188 		i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);  in i915_irq_handler()
4191 	pmu_irq_stats(dev_priv, ret);  in i915_irq_handler()
4193 	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);  in i915_irq_handler()
4198 static void i965_irq_reset(struct drm_i915_private *dev_priv)  in i965_irq_reset()  argument
4200 	struct intel_uncore *uncore = &dev_priv->uncore;  in i965_irq_reset()
4202 	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);  in i965_irq_reset()
4203 …intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT…  in i965_irq_reset()
4205 	i9xx_pipestat_irq_reset(dev_priv);  in i965_irq_reset()
4208 	dev_priv->irq_mask = ~0u;  in i965_irq_reset()
4211 static void i965_irq_postinstall(struct drm_i915_private *dev_priv)  in i965_irq_postinstall()  argument
4213 	struct intel_uncore *uncore = &dev_priv->uncore;  in i965_irq_postinstall()
4221 	if (IS_G4X(dev_priv)) {  in i965_irq_postinstall()
4230 	intel_uncore_write(&dev_priv->uncore, EMR, error_mask);  in i965_irq_postinstall()
4233 	dev_priv->irq_mask =  in i965_irq_postinstall()
4248 	if (IS_G4X(dev_priv))  in i965_irq_postinstall()
4251 	GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);  in i965_irq_postinstall()
4255 	spin_lock_irq(&dev_priv->irq_lock);  in i965_irq_postinstall()
4256 	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);  in i965_irq_postinstall()
4257 	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);  in i965_irq_postinstall()
4258 	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);  in i965_irq_postinstall()
4259 	spin_unlock_irq(&dev_priv->irq_lock);  in i965_irq_postinstall()
4261 	i915_enable_asle_pipestat(dev_priv);  in i965_irq_postinstall()
4264 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)  in i915_hpd_irq_setup()  argument
4268 	lockdep_assert_held(&dev_priv->irq_lock);  in i915_hpd_irq_setup()
4272 	hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);  in i915_hpd_irq_setup()
4277 	if (IS_G4X(dev_priv))  in i915_hpd_irq_setup()
4282 	i915_hotplug_interrupt_update_locked(dev_priv,  in i915_hpd_irq_setup()
4291 	struct drm_i915_private *dev_priv = arg;  in i965_irq_handler()  local
4294 	if (!intel_irqs_enabled(dev_priv))  in i965_irq_handler()
4298 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);  in i965_irq_handler()
4306 		iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);  in i965_irq_handler()
4313 			hotplug_status = i9xx_hpd_irq_ack(dev_priv);  in i965_irq_handler()
4317 		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);  in i965_irq_handler()
4320 			i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);  in i965_irq_handler()
4322 		intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);  in i965_irq_handler()
4325 			intel_engine_cs_irq(dev_priv->gt.engine[RCS0],  in i965_irq_handler()
4329 			intel_engine_cs_irq(dev_priv->gt.engine[VCS0],  in i965_irq_handler()
4333 			i9xx_error_irq_handler(dev_priv, eir, eir_stuck);  in i965_irq_handler()
4336 			i9xx_hpd_irq_handler(dev_priv, hotplug_status);  in i965_irq_handler()
4338 		i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);  in i965_irq_handler()
4341 	pmu_irq_stats(dev_priv, IRQ_HANDLED);  in i965_irq_handler()
4343 	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);  in i965_irq_handler()
4369 void intel_irq_init(struct drm_i915_private *dev_priv)  in intel_irq_init()  argument
4371 	struct drm_device *dev = &dev_priv->drm;  in intel_irq_init()
4374 	INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work);  in intel_irq_init()
4376 		dev_priv->l3_parity.remap_info[i] = NULL;  in intel_irq_init()
4379 	if (HAS_GT_UC(dev_priv) && GRAPHICS_VER(dev_priv) < 11)  in intel_irq_init()
4380 		dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16;  in intel_irq_init()
4382 	if (!HAS_DISPLAY(dev_priv))  in intel_irq_init()
4385 	intel_hpd_init_pins(dev_priv);  in intel_irq_init()
4387 	intel_hpd_init_work(dev_priv);  in intel_irq_init()
4397 	dev_priv->display_irqs_enabled = true;  in intel_irq_init()
4398 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_irq_init()
4399 		dev_priv->display_irqs_enabled = false;  in intel_irq_init()
4401 	dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;  in intel_irq_init()
4408 	dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);  in intel_irq_init()
4410 	if (HAS_GMCH(dev_priv)) {  in intel_irq_init()
4411 		if (I915_HAS_HOTPLUG(dev_priv))  in intel_irq_init()
4412 			dev_priv->hotplug_funcs = &i915_hpd_funcs;  in intel_irq_init()
4414 		if (HAS_PCH_DG1(dev_priv))  in intel_irq_init()
4415 			dev_priv->hotplug_funcs = &dg1_hpd_funcs;  in intel_irq_init()
4416 		else if (DISPLAY_VER(dev_priv) >= 11)  in intel_irq_init()
4417 			dev_priv->hotplug_funcs = &gen11_hpd_funcs;  in intel_irq_init()
4418 		else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))  in intel_irq_init()
4419 			dev_priv->hotplug_funcs = &bxt_hpd_funcs;  in intel_irq_init()
4420 		else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)  in intel_irq_init()
4421 			dev_priv->hotplug_funcs = &icp_hpd_funcs;  in intel_irq_init()
4422 		else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)  in intel_irq_init()
4423 			dev_priv->hotplug_funcs = &spt_hpd_funcs;  in intel_irq_init()
4425 			dev_priv->hotplug_funcs = &ilk_hpd_funcs;  in intel_irq_init()
4443 static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)  in intel_irq_handler()  argument
4445 	if (HAS_GMCH(dev_priv)) {  in intel_irq_handler()
4446 		if (IS_CHERRYVIEW(dev_priv))  in intel_irq_handler()
4448 		else if (IS_VALLEYVIEW(dev_priv))  in intel_irq_handler()
4450 		else if (GRAPHICS_VER(dev_priv) == 4)  in intel_irq_handler()
4452 		else if (GRAPHICS_VER(dev_priv) == 3)  in intel_irq_handler()
4457 		if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10))  in intel_irq_handler()
4459 		else if (GRAPHICS_VER(dev_priv) >= 11)  in intel_irq_handler()
4461 		else if (GRAPHICS_VER(dev_priv) >= 8)  in intel_irq_handler()
4468 static void intel_irq_reset(struct drm_i915_private *dev_priv)  in intel_irq_reset()  argument
4470 	if (HAS_GMCH(dev_priv)) {  in intel_irq_reset()
4471 		if (IS_CHERRYVIEW(dev_priv))  in intel_irq_reset()
4472 			cherryview_irq_reset(dev_priv);  in intel_irq_reset()
4473 		else if (IS_VALLEYVIEW(dev_priv))  in intel_irq_reset()
4474 			valleyview_irq_reset(dev_priv);  in intel_irq_reset()
4475 		else if (GRAPHICS_VER(dev_priv) == 4)  in intel_irq_reset()
4476 			i965_irq_reset(dev_priv);  in intel_irq_reset()
4477 		else if (GRAPHICS_VER(dev_priv) == 3)  in intel_irq_reset()
4478 			i915_irq_reset(dev_priv);  in intel_irq_reset()
4480 			i8xx_irq_reset(dev_priv);  in intel_irq_reset()
4482 		if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10))  in intel_irq_reset()
4483 			dg1_irq_reset(dev_priv);  in intel_irq_reset()
4484 		else if (GRAPHICS_VER(dev_priv) >= 11)  in intel_irq_reset()
4485 			gen11_irq_reset(dev_priv);  in intel_irq_reset()
4486 		else if (GRAPHICS_VER(dev_priv) >= 8)  in intel_irq_reset()
4487 			gen8_irq_reset(dev_priv);  in intel_irq_reset()
4489 			ilk_irq_reset(dev_priv);  in intel_irq_reset()
4493 static void intel_irq_postinstall(struct drm_i915_private *dev_priv)  in intel_irq_postinstall()  argument
4495 	if (HAS_GMCH(dev_priv)) {  in intel_irq_postinstall()
4496 		if (IS_CHERRYVIEW(dev_priv))  in intel_irq_postinstall()
4497 			cherryview_irq_postinstall(dev_priv);  in intel_irq_postinstall()
4498 		else if (IS_VALLEYVIEW(dev_priv))  in intel_irq_postinstall()
4499 			valleyview_irq_postinstall(dev_priv);  in intel_irq_postinstall()
4500 		else if (GRAPHICS_VER(dev_priv) == 4)  in intel_irq_postinstall()
4501 			i965_irq_postinstall(dev_priv);  in intel_irq_postinstall()
4502 		else if (GRAPHICS_VER(dev_priv) == 3)  in intel_irq_postinstall()
4503 			i915_irq_postinstall(dev_priv);  in intel_irq_postinstall()
4505 			i8xx_irq_postinstall(dev_priv);  in intel_irq_postinstall()
4507 		if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10))  in intel_irq_postinstall()
4508 			dg1_irq_postinstall(dev_priv);  in intel_irq_postinstall()
4509 		else if (GRAPHICS_VER(dev_priv) >= 11)  in intel_irq_postinstall()
4510 			gen11_irq_postinstall(dev_priv);  in intel_irq_postinstall()
4511 		else if (GRAPHICS_VER(dev_priv) >= 8)  in intel_irq_postinstall()
4512 			gen8_irq_postinstall(dev_priv);  in intel_irq_postinstall()
4514 			ilk_irq_postinstall(dev_priv);  in intel_irq_postinstall()
4529 int intel_irq_install(struct drm_i915_private *dev_priv)  in intel_irq_install()  argument
4531 	int irq = to_pci_dev(dev_priv->drm.dev)->irq;  in intel_irq_install()
4539 	dev_priv->runtime_pm.irqs_enabled = true;  in intel_irq_install()
4541 	dev_priv->irq_enabled = true;  in intel_irq_install()
4543 	intel_irq_reset(dev_priv);  in intel_irq_install()
4545 	ret = request_irq(irq, intel_irq_handler(dev_priv),  in intel_irq_install()
4546 			  IRQF_SHARED, DRIVER_NAME, dev_priv);  in intel_irq_install()
4548 		dev_priv->irq_enabled = false;  in intel_irq_install()
4552 	intel_irq_postinstall(dev_priv);  in intel_irq_install()
4564 void intel_irq_uninstall(struct drm_i915_private *dev_priv)  in intel_irq_uninstall()  argument
4566 	int irq = to_pci_dev(dev_priv->drm.dev)->irq;  in intel_irq_uninstall()
4574 	if (!dev_priv->irq_enabled)  in intel_irq_uninstall()
4577 	dev_priv->irq_enabled = false;  in intel_irq_uninstall()
4579 	intel_irq_reset(dev_priv);  in intel_irq_uninstall()
4581 	free_irq(irq, dev_priv);  in intel_irq_uninstall()
4583 	intel_hpd_cancel_work(dev_priv);  in intel_irq_uninstall()
4584 	dev_priv->runtime_pm.irqs_enabled = false;  in intel_irq_uninstall()
4594 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)  in intel_runtime_pm_disable_interrupts()  argument
4596 	intel_irq_reset(dev_priv);  in intel_runtime_pm_disable_interrupts()
4597 	dev_priv->runtime_pm.irqs_enabled = false;  in intel_runtime_pm_disable_interrupts()
4598 	intel_synchronize_irq(dev_priv);  in intel_runtime_pm_disable_interrupts()
4608 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)  in intel_runtime_pm_enable_interrupts()  argument
4610 	dev_priv->runtime_pm.irqs_enabled = true;  in intel_runtime_pm_enable_interrupts()
4611 	intel_irq_reset(dev_priv);  in intel_runtime_pm_enable_interrupts()
4612 	intel_irq_postinstall(dev_priv);  in intel_runtime_pm_enable_interrupts()
4615 bool intel_irqs_enabled(struct drm_i915_private *dev_priv)  in intel_irqs_enabled()  argument
4617 	return dev_priv->runtime_pm.irqs_enabled;  in intel_irqs_enabled()

Last Index update Fri Sep 05 17:56:23 CST 2025