Lines Matching refs:ddb
4059 struct skl_ddb_entry *ddb) in skl_ddb_entry_for_slices() argument
4064 ddb->start = 0; in skl_ddb_entry_for_slices()
4065 ddb->end = 0; in skl_ddb_entry_for_slices()
4069 ddb->start = (ffs(slice_mask) - 1) * slice_size; in skl_ddb_entry_for_slices()
4070 ddb->end = fls(slice_mask) * slice_size; in skl_ddb_entry_for_slices()
4072 WARN_ON(ddb->start >= ddb->end); in skl_ddb_entry_for_slices()
4073 WARN_ON(ddb->end > INTEL_INFO(dev_priv)->dbuf.size); in skl_ddb_entry_for_slices()
4078 struct skl_ddb_entry ddb; in mbus_ddb_offset() local
4085 skl_ddb_entry_for_slices(i915, slice_mask, &ddb); in mbus_ddb_offset()
4087 return ddb.start; in mbus_ddb_offset()
4189 new_dbuf_state->ddb[pipe].start = 0; in skl_crtc_allocate_ddb()
4190 new_dbuf_state->ddb[pipe].end = 0; in skl_crtc_allocate_ddb()
4206 new_dbuf_state->ddb[pipe].start = ddb_slices.start - mbus_offset + start; in skl_crtc_allocate_ddb()
4207 new_dbuf_state->ddb[pipe].end = ddb_slices.start - mbus_offset + end; in skl_crtc_allocate_ddb()
4210 skl_ddb_entry_equal(&old_dbuf_state->ddb[pipe], in skl_crtc_allocate_ddb()
4211 &new_dbuf_state->ddb[pipe])) in skl_crtc_allocate_ddb()
4226 crtc_state->wm.skl.ddb.start = mbus_offset + new_dbuf_state->ddb[pipe].start; in skl_crtc_allocate_ddb()
4227 crtc_state->wm.skl.ddb.end = mbus_offset + new_dbuf_state->ddb[pipe].end; in skl_crtc_allocate_ddb()
4233 old_dbuf_state->ddb[pipe].start, old_dbuf_state->ddb[pipe].end, in skl_crtc_allocate_ddb()
4234 new_dbuf_state->ddb[pipe].start, new_dbuf_state->ddb[pipe].end, in skl_crtc_allocate_ddb()
5106 const struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe]; in skl_allocate_plane_ddb()
5948 const struct skl_ddb_entry *ddb = in skl_write_cursor_wm() local
5967 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), ddb); in skl_write_cursor_wm()
6018 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, in skl_ddb_allocation_overlaps() argument
6026 skl_ddb_entries_overlap(ddb, &entries[i])) in skl_ddb_allocation_overlaps()
6615 memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe])); in skl_wm_get_hw_state()
6626 skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_y); in skl_wm_get_hw_state()
6627 skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_uv); in skl_wm_get_hw_state()
6640 crtc_state->wm.skl.ddb.start = mbus_offset + dbuf_state->ddb[pipe].start; in skl_wm_get_hw_state()
6641 crtc_state->wm.skl.ddb.end = mbus_offset + dbuf_state->ddb[pipe].end; in skl_wm_get_hw_state()
6646 dbuf_state->slices[pipe], dbuf_state->ddb[pipe].start, in skl_wm_get_hw_state()
6647 dbuf_state->ddb[pipe].end, dbuf_state->active_pipes, in skl_wm_get_hw_state()