Lines Matching refs:g4x
476 dev_priv->wm.g4x.cxsr = enable; in intel_set_memory_cxsr()
1211 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; in g4x_raw_plane_wm_set()
1230 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; in g4x_raw_fbc_wm_set()
1261 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; in g4x_raw_plane_wm_compute()
1303 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id], in g4x_raw_plane_wm_compute()
1304 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id], in g4x_raw_plane_wm_compute()
1305 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]); in g4x_raw_plane_wm_compute()
1310 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc, in g4x_raw_plane_wm_compute()
1311 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc); in g4x_raw_plane_wm_compute()
1320 const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; in g4x_raw_plane_wm_is_valid()
1386 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal; in g4x_compute_pipe_wm()
1414 raw = &crtc_state->wm.g4x.raw[level]; in g4x_compute_pipe_wm()
1422 raw = &crtc_state->wm.g4x.raw[level]; in g4x_compute_pipe_wm()
1433 raw = &crtc_state->wm.g4x.raw[level]; in g4x_compute_pipe_wm()
1469 struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate; in g4x_compute_intermediate_wm()
1470 const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal; in g4x_compute_intermediate_wm()
1471 const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal; in g4x_compute_intermediate_wm()
1554 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x; in g4x_merge_wm()
1576 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x; in g4x_merge_wm()
1589 struct g4x_wm_values *old_wm = &dev_priv->wm.g4x; in g4x_program_watermarks()
1616 crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate; in g4x_initial_watermarks()
1632 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal; in g4x_optimize_watermarks()
6806 struct g4x_wm_values *wm = &dev_priv->wm.g4x; in g4x_wm_get_hw_state()
6816 struct g4x_wm_state *active = &crtc->wm.active.g4x; in g4x_wm_get_hw_state()
6842 raw = &crtc_state->wm.g4x.raw[level]; in g4x_wm_get_hw_state()
6850 raw = &crtc_state->wm.g4x.raw[level]; in g4x_wm_get_hw_state()
6860 raw = &crtc_state->wm.g4x.raw[level]; in g4x_wm_get_hw_state()
6873 crtc_state->wm.g4x.optimal = *active; in g4x_wm_get_hw_state()
6874 crtc_state->wm.g4x.intermediate = *active; in g4x_wm_get_hw_state()
6908 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal; in g4x_wm_sanitize()
6917 &crtc_state->wm.g4x.raw[level]; in g4x_wm_sanitize()
6926 &crtc_state->wm.g4x.raw[level]; in g4x_wm_sanitize()
6940 crtc_state->wm.g4x.intermediate = in g4x_wm_sanitize()
6941 crtc_state->wm.g4x.optimal; in g4x_wm_sanitize()
6942 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal; in g4x_wm_sanitize()
7907 CG_FUNCS(g4x);