Lines Matching refs:plane_id
1105 static int g4x_plane_fifo_size(enum plane_id plane_id, int level) in g4x_plane_fifo_size() argument
1121 switch (plane_id) { in g4x_plane_fifo_size()
1129 MISSING_CASE(plane_id); in g4x_plane_fifo_size()
1205 int level, enum plane_id plane_id, u16 value) in g4x_raw_plane_wm_set() argument
1213 dirty |= raw->plane[plane_id] != value; in g4x_raw_plane_wm_set()
1214 raw->plane[plane_id] = value; in g4x_raw_plane_wm_set()
1249 enum plane_id plane_id = plane->id; in g4x_raw_plane_wm_compute() local
1254 dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0); in g4x_raw_plane_wm_compute()
1255 if (plane_id == PLANE_PRIMARY) in g4x_raw_plane_wm_compute()
1265 max_wm = g4x_plane_fifo_size(plane_id, level); in g4x_raw_plane_wm_compute()
1270 dirty |= raw->plane[plane_id] != wm; in g4x_raw_plane_wm_compute()
1271 raw->plane[plane_id] = wm; in g4x_raw_plane_wm_compute()
1273 if (plane_id != PLANE_PRIMARY || in g4x_raw_plane_wm_compute()
1278 raw->plane[plane_id]); in g4x_raw_plane_wm_compute()
1293 dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX); in g4x_raw_plane_wm_compute()
1295 if (plane_id == PLANE_PRIMARY) in g4x_raw_plane_wm_compute()
1303 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id], in g4x_raw_plane_wm_compute()
1304 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id], in g4x_raw_plane_wm_compute()
1305 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]); in g4x_raw_plane_wm_compute()
1307 if (plane_id == PLANE_PRIMARY) in g4x_raw_plane_wm_compute()
1318 enum plane_id plane_id, int level) in g4x_raw_plane_wm_is_valid() argument
1322 return raw->plane[plane_id] <= g4x_plane_fifo_size(plane_id, level); in g4x_raw_plane_wm_is_valid()
1343 enum plane_id plane_id; in g4x_invalidate_wms() local
1345 for_each_plane_id_on_crtc(crtc, plane_id) in g4x_invalidate_wms()
1346 wm_state->wm.plane[plane_id] = USHRT_MAX; in g4x_invalidate_wms()
1392 enum plane_id plane_id; in g4x_compute_pipe_wm() local
1415 for_each_plane_id_on_crtc(crtc, plane_id) in g4x_compute_pipe_wm()
1416 wm_state->wm.plane[plane_id] = raw->plane[plane_id]; in g4x_compute_pipe_wm()
1472 enum plane_id plane_id; in g4x_compute_intermediate_wm() local
1489 for_each_plane_id_on_crtc(crtc, plane_id) { in g4x_compute_intermediate_wm()
1490 intermediate->wm.plane[plane_id] = in g4x_compute_intermediate_wm()
1491 max(optimal->wm.plane[plane_id], in g4x_compute_intermediate_wm()
1492 active->wm.plane[plane_id]); in g4x_compute_intermediate_wm()
1494 drm_WARN_ON(&dev_priv->drm, intermediate->wm.plane[plane_id] > in g4x_compute_intermediate_wm()
1495 g4x_plane_fifo_size(plane_id, G4X_WM_LEVEL_NORMAL)); in g4x_compute_intermediate_wm()
1724 enum plane_id plane_id; in vlv_compute_fifo() local
1748 for_each_plane_id_on_crtc(crtc, plane_id) { in vlv_compute_fifo()
1751 if ((active_planes & BIT(plane_id)) == 0) { in vlv_compute_fifo()
1752 fifo_state->plane[plane_id] = 0; in vlv_compute_fifo()
1756 rate = raw->plane[plane_id]; in vlv_compute_fifo()
1757 fifo_state->plane[plane_id] = fifo_size * rate / total_rate; in vlv_compute_fifo()
1758 fifo_left -= fifo_state->plane[plane_id]; in vlv_compute_fifo()
1769 for_each_plane_id_on_crtc(crtc, plane_id) { in vlv_compute_fifo()
1775 if ((active_planes & BIT(plane_id)) == 0) in vlv_compute_fifo()
1779 fifo_state->plane[plane_id] += plane_extra; in vlv_compute_fifo()
1801 enum plane_id plane_id; in vlv_invalidate_wms() local
1803 for_each_plane_id_on_crtc(crtc, plane_id) in vlv_invalidate_wms()
1804 wm_state->wm[level].plane[plane_id] = USHRT_MAX; in vlv_invalidate_wms()
1824 int level, enum plane_id plane_id, u16 value) in vlv_raw_plane_wm_set() argument
1833 dirty |= raw->plane[plane_id] != value; in vlv_raw_plane_wm_set()
1834 raw->plane[plane_id] = value; in vlv_raw_plane_wm_set()
1845 enum plane_id plane_id = plane->id; in vlv_raw_plane_wm_compute() local
1851 dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0); in vlv_raw_plane_wm_compute()
1858 int max_wm = plane_id == PLANE_CURSOR ? 63 : 511; in vlv_raw_plane_wm_compute()
1863 dirty |= raw->plane[plane_id] != wm; in vlv_raw_plane_wm_compute()
1864 raw->plane[plane_id] = wm; in vlv_raw_plane_wm_compute()
1868 dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX); in vlv_raw_plane_wm_compute()
1875 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id], in vlv_raw_plane_wm_compute()
1876 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id], in vlv_raw_plane_wm_compute()
1877 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]); in vlv_raw_plane_wm_compute()
1883 enum plane_id plane_id, int level) in vlv_raw_plane_wm_is_valid() argument
1890 return raw->plane[plane_id] <= fifo_state->plane[plane_id]; in vlv_raw_plane_wm_is_valid()
1916 enum plane_id plane_id; in vlv_compute_pipe_wm() local
1976 for_each_plane_id_on_crtc(crtc, plane_id) { in vlv_compute_pipe_wm()
1977 wm_state->wm[level].plane[plane_id] = in vlv_compute_pipe_wm()
1978 vlv_invert_wm_value(raw->plane[plane_id], in vlv_compute_pipe_wm()
1979 fifo_state->plane[plane_id]); in vlv_compute_pipe_wm()
2131 enum plane_id plane_id; in vlv_compute_intermediate_wm() local
2133 for_each_plane_id_on_crtc(crtc, plane_id) { in vlv_compute_intermediate_wm()
2134 intermediate->wm[level].plane[plane_id] = in vlv_compute_intermediate_wm()
2135 min(optimal->wm[level].plane[plane_id], in vlv_compute_intermediate_wm()
2136 active->wm[level].plane[plane_id]); in vlv_compute_intermediate_wm()
3897 enum plane_id plane_id; in skl_crtc_can_enable_sagv() local
3909 for_each_plane_id_on_crtc(crtc, plane_id) { in skl_crtc_can_enable_sagv()
3911 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_can_enable_sagv()
3931 for_each_plane_id_on_crtc(crtc, plane_id) { in skl_crtc_can_enable_sagv()
3933 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_can_enable_sagv()
3949 enum plane_id plane_id; in tgl_crtc_can_enable_sagv() local
3954 for_each_plane_id_on_crtc(crtc, plane_id) { in tgl_crtc_can_enable_sagv()
3956 &crtc_state->wm.skl.optimal.planes[plane_id]; in tgl_crtc_can_enable_sagv()
4295 const enum plane_id plane_id, in skl_ddb_get_hw_plane_state() argument
4303 if (plane_id == PLANE_CURSOR) { in skl_ddb_get_hw_plane_state()
4309 val = intel_uncore_read(&dev_priv->uncore, PLANE_CTL(pipe, plane_id)); in skl_ddb_get_hw_plane_state()
4318 val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id)); in skl_ddb_get_hw_plane_state()
4321 val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id)); in skl_ddb_get_hw_plane_state()
4322 val2 = intel_uncore_read(&dev_priv->uncore, PLANE_NV12_BUF_CFG(pipe, plane_id)); in skl_ddb_get_hw_plane_state()
4341 enum plane_id plane_id; in skl_pipe_ddb_get_hw_state() local
4348 for_each_plane_id_on_crtc(crtc, plane_id) in skl_pipe_ddb_get_hw_state()
4350 plane_id, in skl_pipe_ddb_get_hw_state()
4351 &ddb_y[plane_id], in skl_pipe_ddb_get_hw_state()
4352 &ddb_uv[plane_id]); in skl_pipe_ddb_get_hw_state()
4964 enum plane_id plane_id; in skl_get_total_relative_data_rate() local
4972 plane_id = plane->id; in skl_get_total_relative_data_rate()
4975 crtc_state->plane_data_rate[plane_id] = in skl_get_total_relative_data_rate()
4979 crtc_state->uv_plane_data_rate[plane_id] = in skl_get_total_relative_data_rate()
4983 for_each_plane_id_on_crtc(crtc, plane_id) { in skl_get_total_relative_data_rate()
4984 total_data_rate += crtc_state->plane_data_rate[plane_id]; in skl_get_total_relative_data_rate()
4985 total_data_rate += crtc_state->uv_plane_data_rate[plane_id]; in skl_get_total_relative_data_rate()
5000 enum plane_id plane_id; in icl_get_total_relative_data_rate() local
5008 plane_id = plane->id; in icl_get_total_relative_data_rate()
5011 crtc_state->plane_data_rate[plane_id] = in icl_get_total_relative_data_rate()
5014 enum plane_id y_plane_id; in icl_get_total_relative_data_rate()
5031 crtc_state->plane_data_rate[plane_id] = in icl_get_total_relative_data_rate()
5036 for_each_plane_id_on_crtc(crtc, plane_id) in icl_get_total_relative_data_rate()
5037 total_data_rate += crtc_state->plane_data_rate[plane_id]; in icl_get_total_relative_data_rate()
5044 enum plane_id plane_id, in skl_plane_wm_level() argument
5047 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; in skl_plane_wm_level()
5057 enum plane_id plane_id) in skl_plane_trans_wm() argument
5059 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; in skl_plane_trans_wm()
5112 enum plane_id plane_id; in skl_allocate_plane_ddb() local
5150 for_each_plane_id_on_crtc(crtc, plane_id) { in skl_allocate_plane_ddb()
5152 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_allocate_plane_ddb()
5154 if (plane_id == PLANE_CURSOR) { in skl_allocate_plane_ddb()
5187 for_each_plane_id_on_crtc(crtc, plane_id) { in skl_allocate_plane_ddb()
5189 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_allocate_plane_ddb()
5193 if (plane_id == PLANE_CURSOR) in skl_allocate_plane_ddb()
5203 rate = crtc_state->plane_data_rate[plane_id]; in skl_allocate_plane_ddb()
5207 total[plane_id] = wm->wm[level].min_ddb_alloc + extra; in skl_allocate_plane_ddb()
5214 rate = crtc_state->uv_plane_data_rate[plane_id]; in skl_allocate_plane_ddb()
5218 uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra; in skl_allocate_plane_ddb()
5226 for_each_plane_id_on_crtc(crtc, plane_id) { in skl_allocate_plane_ddb()
5228 &crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_allocate_plane_ddb()
5230 &crtc_state->wm.skl.plane_ddb_uv[plane_id]; in skl_allocate_plane_ddb()
5232 if (plane_id == PLANE_CURSOR) in skl_allocate_plane_ddb()
5237 DISPLAY_VER(dev_priv) >= 11 && uv_total[plane_id]); in skl_allocate_plane_ddb()
5240 if (total[plane_id]) { in skl_allocate_plane_ddb()
5242 start += total[plane_id]; in skl_allocate_plane_ddb()
5246 if (uv_total[plane_id]) { in skl_allocate_plane_ddb()
5248 start += uv_total[plane_id]; in skl_allocate_plane_ddb()
5260 for_each_plane_id_on_crtc(crtc, plane_id) { in skl_allocate_plane_ddb()
5262 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_allocate_plane_ddb()
5265 total[plane_id], uv_total[plane_id]); in skl_allocate_plane_ddb()
5284 for_each_plane_id_on_crtc(crtc, plane_id) { in skl_allocate_plane_ddb()
5286 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_allocate_plane_ddb()
5288 skl_check_wm_level(&wm->trans_wm, total[plane_id]); in skl_allocate_plane_ddb()
5289 skl_check_wm_level(&wm->sagv.wm0, total[plane_id]); in skl_allocate_plane_ddb()
5290 skl_check_wm_level(&wm->sagv.trans_wm, total[plane_id]); in skl_allocate_plane_ddb()
5717 enum plane_id plane_id, int color_plane) in skl_build_plane_wm_single() argument
5721 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id]; in skl_build_plane_wm_single()
5747 enum plane_id plane_id) in skl_build_plane_wm_uv() argument
5749 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id]; in skl_build_plane_wm_uv()
5770 enum plane_id plane_id = plane->id; in skl_build_plane_wm() local
5771 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id]; in skl_build_plane_wm()
5781 plane_id, 0); in skl_build_plane_wm()
5787 plane_id); in skl_build_plane_wm()
5800 enum plane_id plane_id = plane->id; in icl_build_plane_wm() local
5801 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id]; in icl_build_plane_wm()
5812 enum plane_id y_plane_id = plane_state->planar_linked_plane->id; in icl_build_plane_wm()
5825 plane_id, 1); in icl_build_plane_wm()
5830 plane_id, 0); in icl_build_plane_wm()
5902 enum plane_id plane_id = plane->id; in skl_write_plane_wm() local
5905 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; in skl_write_plane_wm()
5907 &crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_write_plane_wm()
5909 &crtc_state->wm.skl.plane_ddb_uv[plane_id]; in skl_write_plane_wm()
5912 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level), in skl_write_plane_wm()
5913 skl_plane_wm_level(pipe_wm, plane_id, level)); in skl_write_plane_wm()
5915 skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id), in skl_write_plane_wm()
5916 skl_plane_trans_wm(pipe_wm, plane_id)); in skl_write_plane_wm()
5919 skl_write_wm_level(dev_priv, PLANE_WM_SAGV(pipe, plane_id), in skl_write_plane_wm()
5921 skl_write_wm_level(dev_priv, PLANE_WM_SAGV_TRANS(pipe, plane_id), in skl_write_plane_wm()
5927 PLANE_BUF_CFG(pipe, plane_id), ddb_y); in skl_write_plane_wm()
5935 PLANE_BUF_CFG(pipe, plane_id), ddb_y); in skl_write_plane_wm()
5937 PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_uv); in skl_write_plane_wm()
5945 enum plane_id plane_id = plane->id; in skl_write_cursor_wm() local
5949 &crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_write_cursor_wm()
5953 skl_plane_wm_level(pipe_wm, plane_id, level)); in skl_write_cursor_wm()
5956 skl_plane_trans_wm(pipe_wm, plane_id)); in skl_write_cursor_wm()
5959 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; in skl_write_cursor_wm()
6044 enum plane_id plane_id = plane->id; in skl_ddb_add_affected_planes() local
6046 if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id], in skl_ddb_add_affected_planes()
6047 &new_crtc_state->wm.skl.plane_ddb_y[plane_id]) && in skl_ddb_add_affected_planes()
6048 skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_uv[plane_id], in skl_ddb_add_affected_planes()
6049 &new_crtc_state->wm.skl.plane_ddb_uv[plane_id])) in skl_ddb_add_affected_planes()
6056 new_crtc_state->update_planes |= BIT(plane_id); in skl_ddb_add_affected_planes()
6213 enum plane_id plane_id = plane->id; in skl_print_wm_changes() local
6216 old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_print_wm_changes()
6217 new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_print_wm_changes()
6230 enum plane_id plane_id = plane->id; in skl_print_wm_changes() local
6233 old_wm = &old_pipe_wm->planes[plane_id]; in skl_print_wm_changes()
6234 new_wm = &new_pipe_wm->planes[plane_id]; in skl_print_wm_changes()
6391 enum plane_id plane_id = plane->id; in skl_wm_add_affected_planes() local
6411 new_crtc_state->update_planes |= BIT(plane_id); in skl_wm_add_affected_planes()
6547 enum plane_id plane_id; in skl_pipe_wm_get_hw_state() local
6552 for_each_plane_id_on_crtc(crtc, plane_id) { in skl_pipe_wm_get_hw_state()
6553 struct skl_plane_wm *wm = &out->planes[plane_id]; in skl_pipe_wm_get_hw_state()
6556 if (plane_id != PLANE_CURSOR) in skl_pipe_wm_get_hw_state()
6557 val = intel_uncore_read(&dev_priv->uncore, PLANE_WM(pipe, plane_id, level)); in skl_pipe_wm_get_hw_state()
6564 if (plane_id != PLANE_CURSOR) in skl_pipe_wm_get_hw_state()
6565 val = intel_uncore_read(&dev_priv->uncore, PLANE_WM_TRANS(pipe, plane_id)); in skl_pipe_wm_get_hw_state()
6572 if (plane_id != PLANE_CURSOR) in skl_pipe_wm_get_hw_state()
6574 PLANE_WM_SAGV(pipe, plane_id)); in skl_pipe_wm_get_hw_state()
6581 if (plane_id != PLANE_CURSOR) in skl_pipe_wm_get_hw_state()
6583 PLANE_WM_SAGV_TRANS(pipe, plane_id)); in skl_pipe_wm_get_hw_state()
6610 enum plane_id plane_id; in skl_wm_get_hw_state() local
6617 for_each_plane_id_on_crtc(crtc, plane_id) { in skl_wm_get_hw_state()
6619 &crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_wm_get_hw_state()
6621 &crtc_state->wm.skl.plane_ddb_uv[plane_id]; in skl_wm_get_hw_state()
6624 plane_id, ddb_y, ddb_uv); in skl_wm_get_hw_state()
6819 enum plane_id plane_id; in g4x_wm_get_hw_state() local
6829 for_each_plane_id_on_crtc(crtc, plane_id) { in g4x_wm_get_hw_state()
6830 active->wm.plane[plane_id] = in g4x_wm_get_hw_state()
6831 wm->pipe[pipe].plane[plane_id]; in g4x_wm_get_hw_state()
6843 for_each_plane_id_on_crtc(crtc, plane_id) in g4x_wm_get_hw_state()
6844 raw->plane[plane_id] = active->wm.plane[plane_id]; in g4x_wm_get_hw_state()
6868 for_each_plane_id_on_crtc(crtc, plane_id) in g4x_wm_get_hw_state()
6870 plane_id, USHRT_MAX); in g4x_wm_get_hw_state()
6909 enum plane_id plane_id = plane->id; in g4x_wm_sanitize() local
6919 raw->plane[plane_id] = 0; in g4x_wm_sanitize()
6920 wm_state->wm.plane[plane_id] = 0; in g4x_wm_sanitize()
6923 if (plane_id == PLANE_PRIMARY) { in g4x_wm_sanitize()
7003 enum plane_id plane_id; in vlv_wm_get_hw_state() local
7018 for_each_plane_id_on_crtc(crtc, plane_id) { in vlv_wm_get_hw_state()
7019 active->wm[level].plane[plane_id] = in vlv_wm_get_hw_state()
7020 wm->pipe[pipe].plane[plane_id]; in vlv_wm_get_hw_state()
7022 raw->plane[plane_id] = in vlv_wm_get_hw_state()
7023 vlv_invert_wm_value(active->wm[level].plane[plane_id], in vlv_wm_get_hw_state()
7024 fifo_state->plane[plane_id]); in vlv_wm_get_hw_state()
7028 for_each_plane_id_on_crtc(crtc, plane_id) in vlv_wm_get_hw_state()
7030 plane_id, USHRT_MAX); in vlv_wm_get_hw_state()
7067 enum plane_id plane_id = plane->id; in vlv_wm_sanitize() local
7077 raw->plane[plane_id] = 0; in vlv_wm_sanitize()
7079 wm_state->wm[level].plane[plane_id] = in vlv_wm_sanitize()
7080 vlv_invert_wm_value(raw->plane[plane_id], in vlv_wm_sanitize()
7081 fifo_state->plane[plane_id]); in vlv_wm_sanitize()