Lines Matching refs:mmu_write
13 #define mmu_write(reg, data) writel(data, ip->iomem + reg) macro
20 mmu_write(LIMA_MMU_COMMAND, cmd); \
53 mmu_write(LIMA_MMU_INT_MASK, 0); in lima_mmu_irq_handler()
54 mmu_write(LIMA_MMU_INT_CLEAR, status); in lima_mmu_irq_handler()
68 mmu_write(LIMA_MMU_COMMAND, LIMA_MMU_COMMAND_HARD_RESET); in lima_mmu_hw_init()
74 mmu_write(LIMA_MMU_INT_MASK, in lima_mmu_hw_init()
76 mmu_write(LIMA_MMU_DTE_ADDR, dev->empty_vm->pd.dma); in lima_mmu_hw_init()
103 mmu_write(LIMA_MMU_DTE_ADDR, 0xCAFEBABE); in lima_mmu_init()
126 mmu_write(LIMA_MMU_COMMAND, LIMA_MMU_COMMAND_ZAP_CACHE); in lima_mmu_flush_tlb()
138 mmu_write(LIMA_MMU_DTE_ADDR, vm->pd.dma); in lima_mmu_switch_vm()
141 mmu_write(LIMA_MMU_COMMAND, LIMA_MMU_COMMAND_ZAP_CACHE); in lima_mmu_switch_vm()
157 mmu_write(LIMA_MMU_INT_MASK, 0); in lima_mmu_page_fault_resume()
158 mmu_write(LIMA_MMU_DTE_ADDR, 0xCAFEBABE); in lima_mmu_page_fault_resume()
161 mmu_write(LIMA_MMU_INT_MASK, LIMA_MMU_INT_PAGE_FAULT | LIMA_MMU_INT_READ_BUS_ERROR); in lima_mmu_page_fault_resume()
162 mmu_write(LIMA_MMU_DTE_ADDR, dev->empty_vm->pd.dma); in lima_mmu_page_fault_resume()