Lines Matching refs:gpu
25 static inline void set_preempt_state(struct a5xx_gpu *gpu, in set_preempt_state() argument
34 atomic_set(&gpu->preempt_state, new); in set_preempt_state()
40 static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_wptr() argument
52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
56 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) in get_next_ring() argument
61 for (i = 0; i < gpu->nr_rings; i++) { in get_next_ring()
63 struct msm_ringbuffer *ring = gpu->rb[i]; in get_next_ring()
79 struct msm_gpu *gpu = &a5xx_gpu->base.base; in a5xx_preempt_timer() local
80 struct drm_device *dev = gpu->dev; in a5xx_preempt_timer()
85 DRM_DEV_ERROR(dev->dev, "%s: preemption timed out\n", gpu->name); in a5xx_preempt_timer()
86 kthread_queue_work(gpu->worker, &gpu->recover_work); in a5xx_preempt_timer()
90 void a5xx_preempt_trigger(struct msm_gpu *gpu) in a5xx_preempt_trigger() argument
92 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_preempt_trigger()
97 if (gpu->nr_rings == 1) in a5xx_preempt_trigger()
108 ring = get_next_ring(gpu); in a5xx_preempt_trigger()
128 update_wptr(gpu, a5xx_gpu->cur_ring); in a5xx_preempt_trigger()
139 gpu_write64(gpu, REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO, in a5xx_preempt_trigger()
155 gpu_write(gpu, REG_A5XX_CP_CONTEXT_SWITCH_CNTL, 1); in a5xx_preempt_trigger()
158 void a5xx_preempt_irq(struct msm_gpu *gpu) in a5xx_preempt_irq() argument
161 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_preempt_irq()
163 struct drm_device *dev = gpu->dev; in a5xx_preempt_irq()
177 status = gpu_read(gpu, REG_A5XX_CP_CONTEXT_SWITCH_CNTL); in a5xx_preempt_irq()
181 gpu->name); in a5xx_preempt_irq()
182 kthread_queue_work(gpu->worker, &gpu->recover_work); in a5xx_preempt_irq()
189 update_wptr(gpu, a5xx_gpu->cur_ring); in a5xx_preempt_irq()
194 void a5xx_preempt_hw_init(struct msm_gpu *gpu) in a5xx_preempt_hw_init() argument
196 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_preempt_hw_init()
201 a5xx_gpu->cur_ring = gpu->rb[0]; in a5xx_preempt_hw_init()
204 if (gpu->nr_rings == 1) in a5xx_preempt_hw_init()
207 for (i = 0; i < gpu->nr_rings; i++) { in a5xx_preempt_hw_init()
210 a5xx_gpu->preempt[i]->rbase = gpu->rb[i]->iova; in a5xx_preempt_hw_init()
214 gpu_write64(gpu, REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO, in a5xx_preempt_hw_init()
225 struct msm_gpu *gpu = &adreno_gpu->base; in preempt_init_ring() local
231 ptr = msm_gem_kernel_new(gpu->dev, in preempt_init_ring()
233 MSM_BO_WC | MSM_BO_MAP_PRIV, gpu->aspace, &bo, &iova); in preempt_init_ring()
239 counters = msm_gem_kernel_new(gpu->dev, in preempt_init_ring()
241 MSM_BO_WC, gpu->aspace, &counters_bo, &counters_iova); in preempt_init_ring()
243 msm_gem_kernel_put(bo, gpu->aspace); in preempt_init_ring()
268 void a5xx_preempt_fini(struct msm_gpu *gpu) in a5xx_preempt_fini() argument
270 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_preempt_fini()
274 for (i = 0; i < gpu->nr_rings; i++) { in a5xx_preempt_fini()
275 msm_gem_kernel_put(a5xx_gpu->preempt_bo[i], gpu->aspace); in a5xx_preempt_fini()
276 msm_gem_kernel_put(a5xx_gpu->preempt_counters_bo[i], gpu->aspace); in a5xx_preempt_fini()
280 void a5xx_preempt_init(struct msm_gpu *gpu) in a5xx_preempt_init() argument
282 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_preempt_init()
287 if (gpu->nr_rings <= 1) in a5xx_preempt_init()
290 for (i = 0; i < gpu->nr_rings; i++) { in a5xx_preempt_init()
291 if (preempt_init_ring(a5xx_gpu, gpu->rb[i])) { in a5xx_preempt_init()
296 a5xx_preempt_fini(gpu); in a5xx_preempt_init()
297 gpu->nr_rings = 1; in a5xx_preempt_init()