Lines Matching refs:reg_val
45 u32 reg_val; member
199 u32 reg_val, hdcp_int_status; in msm_hdmi_hdcp_irq() local
203 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_INT_CTRL); in msm_hdmi_hdcp_irq()
204 hdcp_int_status = reg_val & HDCP_INT_STATUS_MASK; in msm_hdmi_hdcp_irq()
210 reg_val |= hdcp_int_status << 1; in msm_hdmi_hdcp_irq()
213 reg_val |= HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK; in msm_hdmi_hdcp_irq()
214 hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL, reg_val); in msm_hdmi_hdcp_irq()
228 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS); in msm_hdmi_hdcp_irq()
230 __func__, reg_val); in msm_hdmi_hdcp_irq()
284 u32 reg_val, failure, nack0; in msm_reset_hdcp_ddc_failures() local
288 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_STATUS); in msm_reset_hdcp_ddc_failures()
289 failure = reg_val & HDMI_HDCP_DDC_STATUS_FAILED; in msm_reset_hdcp_ddc_failures()
290 nack0 = reg_val & HDMI_HDCP_DDC_STATUS_NACK0; in msm_reset_hdcp_ddc_failures()
292 reg_val, failure, nack0); in msm_reset_hdcp_ddc_failures()
309 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_CTRL_1); in msm_reset_hdcp_ddc_failures()
310 reg_val |= HDMI_HDCP_DDC_CTRL_1_FAILED_ACK; in msm_reset_hdcp_ddc_failures()
311 hdmi_write(hdmi, REG_HDMI_HDCP_DDC_CTRL_1, reg_val); in msm_reset_hdcp_ddc_failures()
314 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_STATUS); in msm_reset_hdcp_ddc_failures()
315 if (reg_val & HDMI_HDCP_DDC_STATUS_FAILED) in msm_reset_hdcp_ddc_failures()
327 reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL); in msm_reset_hdcp_ddc_failures()
328 reg_val |= HDMI_DDC_CTRL_SW_STATUS_RESET; in msm_reset_hdcp_ddc_failures()
329 hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val); in msm_reset_hdcp_ddc_failures()
333 reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL); in msm_reset_hdcp_ddc_failures()
334 reg_val &= ~HDMI_DDC_CTRL_SW_STATUS_RESET; in msm_reset_hdcp_ddc_failures()
335 hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val); in msm_reset_hdcp_ddc_failures()
338 reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL); in msm_reset_hdcp_ddc_failures()
339 reg_val |= HDMI_DDC_CTRL_SOFT_RESET; in msm_reset_hdcp_ddc_failures()
340 hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val); in msm_reset_hdcp_ddc_failures()
346 reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL); in msm_reset_hdcp_ddc_failures()
347 reg_val &= ~HDMI_DDC_CTRL_SOFT_RESET; in msm_reset_hdcp_ddc_failures()
348 hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val); in msm_reset_hdcp_ddc_failures()
402 u32 reg_val; in msm_hdmi_hdcp_reauth_work() local
412 reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL); in msm_hdmi_hdcp_reauth_work()
413 reg_val &= ~HDMI_HPD_CTRL_ENABLE; in msm_hdmi_hdcp_reauth_work()
414 hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val); in msm_hdmi_hdcp_reauth_work()
434 reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL); in msm_hdmi_hdcp_reauth_work()
435 reg_val |= HDMI_HPD_CTRL_ENABLE; in msm_hdmi_hdcp_reauth_work()
436 hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val); in msm_hdmi_hdcp_reauth_work()
459 u32 reg_val; in msm_hdmi_hdcp_auth_prepare() local
475 reg_val = hdmi_read(hdmi, REG_HDMI_CTRL); in msm_hdmi_hdcp_auth_prepare()
476 reg_val &= ~HDMI_CTRL_ENCRYPTED; in msm_hdmi_hdcp_auth_prepare()
477 hdmi_write(hdmi, REG_HDMI_CTRL, reg_val); in msm_hdmi_hdcp_auth_prepare()
480 reg_val = hdmi_read(hdmi, REG_HDMI_DDC_ARBITRATION); in msm_hdmi_hdcp_auth_prepare()
481 reg_val &= ~HDMI_DDC_ARBITRATION_HW_ARBITRATION; in msm_hdmi_hdcp_auth_prepare()
482 hdmi_write(hdmi, REG_HDMI_DDC_ARBITRATION, reg_val); in msm_hdmi_hdcp_auth_prepare()
501 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DEBUG_CTRL); in msm_hdmi_hdcp_auth_prepare()
502 reg_val &= ~HDMI_HDCP_DEBUG_CTRL_RNG_CIPHER; in msm_hdmi_hdcp_auth_prepare()
503 hdmi_write(hdmi, REG_HDMI_HDCP_DEBUG_CTRL, reg_val); in msm_hdmi_hdcp_auth_prepare()
540 u32 reg_val; in msm_hdmi_hdcp_auth_fail() local
546 reg_val = hdmi_read(hdmi, REG_HDMI_CTRL); in msm_hdmi_hdcp_auth_fail()
547 reg_val &= ~HDMI_CTRL_ENCRYPTED; in msm_hdmi_hdcp_auth_fail()
548 hdmi_write(hdmi, REG_HDMI_CTRL, reg_val); in msm_hdmi_hdcp_auth_fail()
558 u32 reg_val; in msm_hdmi_hdcp_auth_done() local
566 reg_val = hdmi_read(hdmi, REG_HDMI_DDC_ARBITRATION); in msm_hdmi_hdcp_auth_done()
567 reg_val |= HDMI_DDC_ARBITRATION_HW_ARBITRATION; in msm_hdmi_hdcp_auth_done()
568 hdmi_write(hdmi, REG_HDMI_DDC_ARBITRATION, reg_val); in msm_hdmi_hdcp_auth_done()
573 reg_val = hdmi_read(hdmi, REG_HDMI_CTRL); in msm_hdmi_hdcp_auth_done()
574 reg_val |= HDMI_CTRL_ENCRYPTED; in msm_hdmi_hdcp_auth_done()
575 hdmi_write(hdmi, REG_HDMI_CTRL, reg_val); in msm_hdmi_hdcp_auth_done()
1120 u32 reg_val, data, reg; in msm_hdmi_hdcp_write_ksv_fifo() local
1127 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_SHA_STATUS); in msm_hdmi_hdcp_write_ksv_fifo()
1128 DBG("HDCP_SHA_STATUS=%08x", reg_val); in msm_hdmi_hdcp_write_ksv_fifo()
1131 if (reg_val & HDMI_HDCP_SHA_STATUS_COMP_DONE) { in msm_hdmi_hdcp_write_ksv_fifo()
1139 if (!(reg_val & HDMI_HDCP_SHA_STATUS_BLOCK_DONE)) in msm_hdmi_hdcp_write_ksv_fifo()
1157 reg_val = ksv_fifo[i] << 16; in msm_hdmi_hdcp_write_ksv_fifo()
1159 reg_val |= HDMI_HDCP_SHA_DATA_DONE; in msm_hdmi_hdcp_write_ksv_fifo()
1162 data = reg_val; in msm_hdmi_hdcp_write_ksv_fifo()
1307 u32 reg_val; in msm_hdmi_hdcp_on() local
1318 reg_val = hdmi_read(hdmi, REG_HDMI_CTRL); in msm_hdmi_hdcp_on()
1319 reg_val &= ~HDMI_CTRL_ENCRYPTED; in msm_hdmi_hdcp_on()
1320 hdmi_write(hdmi, REG_HDMI_CTRL, reg_val); in msm_hdmi_hdcp_on()
1333 u32 reg_val; in msm_hdmi_hdcp_off() local
1348 reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL); in msm_hdmi_hdcp_off()
1349 reg_val &= ~HDMI_HPD_CTRL_ENABLE; in msm_hdmi_hdcp_off()
1350 hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val); in msm_hdmi_hdcp_off()
1378 reg_val = hdmi_read(hdmi, REG_HDMI_CTRL); in msm_hdmi_hdcp_off()
1379 reg_val &= ~HDMI_CTRL_ENCRYPTED; in msm_hdmi_hdcp_off()
1380 hdmi_write(hdmi, REG_HDMI_CTRL, reg_val); in msm_hdmi_hdcp_off()
1383 reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL); in msm_hdmi_hdcp_off()
1384 reg_val |= HDMI_HPD_CTRL_ENABLE; in msm_hdmi_hdcp_off()
1385 hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val); in msm_hdmi_hdcp_off()