Lines Matching refs:asyh
421 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); in nv50_outp_atomic_check() local
430 asyh->or.bpc = connector->display_info.bpc; in nv50_outp_atomic_check()
503 struct nv50_head_atom *asyh = in nv50_dac_atomic_enable() local
522 core->func->dac->ctrl(core, nv_encoder->or, ctrl, asyh); in nv50_dac_atomic_enable()
523 asyh->or.depth = 0; in nv50_dac_atomic_enable()
1045 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); in nv50_msto_atomic_check() local
1065 asyh->or.bpc = connector->display_info.bpc; in nv50_msto_atomic_check()
1066 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3, in nv50_msto_atomic_check()
1071 asyh->dp.pbn, 0); in nv50_msto_atomic_check()
1075 asyh->dp.tu = slots; in nv50_msto_atomic_check()
1096 struct nv50_head_atom *asyh = in nv50_msto_atomic_enable() local
1118 r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, asyh->dp.pbn, asyh->dp.tu); in nv50_msto_atomic_enable()
1130 mstm->outp->update(mstm->outp, head->base.index, asyh, proto, in nv50_msto_atomic_enable()
1131 nv50_dp_bpc_to_depth(asyh->or.bpc)); in nv50_msto_atomic_enable()
1635 struct nv50_head_atom *asyh, u8 proto, u8 depth) in nv50_sor_update() argument
1640 if (!asyh) { in nv50_sor_update()
1647 asyh->or.depth = depth; in nv50_sor_update()
1650 core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh); in nv50_sor_update()
1703 struct nv50_head_atom *asyh = in nv50_sor_atomic_enable() local
1705 struct drm_display_mode *mode = &asyh->state.adjusted_mode; in nv50_sor_atomic_enable()
1781 if (asyh->or.bpc == 8) in nv50_sor_atomic_enable()
1788 depth = nv50_dp_bpc_to_depth(asyh->or.bpc); in nv50_sor_atomic_enable()
1810 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth); in nv50_sor_atomic_enable()
1955 struct nv50_head_atom *asyh = in nv50_pior_atomic_enable() local
1970 switch (asyh->or.bpc) { in nv50_pior_atomic_enable()
1971 case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break; in nv50_pior_atomic_enable()
1972 case 8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break; in nv50_pior_atomic_enable()
1973 case 6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break; in nv50_pior_atomic_enable()
1974 default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break; in nv50_pior_atomic_enable()
1987 core->func->pior->ctrl(core, nv_encoder->or, ctrl, asyh); in nv50_pior_atomic_enable()
2144 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); in nv50_disp_atomic_commit_tail() local
2148 asyh->clr.mask, asyh->set.mask); in nv50_disp_atomic_commit_tail()
2155 if (asyh->clr.mask) { in nv50_disp_atomic_commit_tail()
2156 nv50_head_flush_clr(head, asyh, atom->flush_disable); in nv50_disp_atomic_commit_tail()
2235 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); in nv50_disp_atomic_commit_tail() local
2239 asyh->set.mask, asyh->clr.mask); in nv50_disp_atomic_commit_tail()
2241 if (asyh->set.mask) { in nv50_disp_atomic_commit_tail()
2242 nv50_head_flush_set(head, asyh); in nv50_disp_atomic_commit_tail()
2286 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); in nv50_disp_atomic_commit_tail() local
2290 asyh->set.mask, asyh->clr.mask); in nv50_disp_atomic_commit_tail()
2292 if (asyh->set.mask) { in nv50_disp_atomic_commit_tail()
2293 nv50_head_flush_set_wndw(head, asyh); in nv50_disp_atomic_commit_tail()
2522 struct nv50_head_atom *asyh; in nv50_disp_atomic_check() local
2533 asyh = nv50_head_atom(new_crtc_state); in nv50_disp_atomic_check()
2534 core->func->head->static_wndw_map(head, asyh); in nv50_disp_atomic_check()