Lines Matching refs:T
71 #define T(t) cfg->timing_10_##t macro
86 switch ((!T(CWL)) * ram->base.type) { in nv50_ram_timing_calc()
88 T(CWL) = T(CL) - 1; in nv50_ram_timing_calc()
91 T(CWL) = ((cur2 & 0xff000000) >> 24) + 1; in nv50_ram_timing_calc()
98 timing[6] = (0x2d + T(CL) - T(CWL) + in nv50_ram_timing_calc()
100 T(CWL) << 8 | in nv50_ram_timing_calc()
101 (0x2f + T(CL) - T(CWL)); in nv50_ram_timing_calc()
104 timing[6] = (0x2b + T(CL) - T(CWL)) << 16 | in nv50_ram_timing_calc()
105 max_t(s8, T(CWL) - 2, 1) << 8 | in nv50_ram_timing_calc()
106 (0x2e + T(CL) - T(CWL)); in nv50_ram_timing_calc()
109 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); in nv50_ram_timing_calc()
110 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in nv50_ram_timing_calc()
111 max_t(u8, T(18), 1) << 16 | in nv50_ram_timing_calc()
112 (T(WTR) + 1 + T(CWL)) << 8 | in nv50_ram_timing_calc()
113 (3 + T(CL) - T(CWL)); in nv50_ram_timing_calc()
114 timing[2] = (T(CWL) - 1) << 24 | in nv50_ram_timing_calc()
115 (T(RRD) << 16) | in nv50_ram_timing_calc()
116 (T(RCDWR) << 8) | in nv50_ram_timing_calc()
117 T(RCDRD); in nv50_ram_timing_calc()
118 timing[3] = (unkt3b - 2 + T(CL)) << 24 | in nv50_ram_timing_calc()
120 (T(CL) - 1) << 8 | in nv50_ram_timing_calc()
121 (T(CL) - 1); in nv50_ram_timing_calc()
123 T(13) << 8 | in nv50_ram_timing_calc()
124 T(13); in nv50_ram_timing_calc()
125 timing[5] = T(RFC) << 24 | in nv50_ram_timing_calc()
126 max_t(u8, T(RCDRD), T(RCDWR)) << 16 | in nv50_ram_timing_calc()
127 T(RP); in nv50_ram_timing_calc()
129 timing[7] = (cur7 & 0xff00ffff) | (T(CL) - 1) << 16; in nv50_ram_timing_calc()
134 timing[5] |= (T(CL) + 3) << 8; in nv50_ram_timing_calc()
135 timing[8] |= (T(CL) - 4); in nv50_ram_timing_calc()
138 timing[5] |= (T(CL) + 2) << 8; in nv50_ram_timing_calc()
139 timing[8] |= (T(CL) - 2); in nv50_ram_timing_calc()
163 T(CL) = (timing[3] & 0xff) + 1; in nv50_ram_timing_read()
167 T(CWL) = T(CL) - 1; in nv50_ram_timing_read()
170 T(CWL) = ((timing[2] & 0xff000000) >> 24) + 1; in nv50_ram_timing_read()
176 T(WR) = ((timing[1] >> 24) & 0xff) - 1 - T(CWL); in nv50_ram_timing_read()
180 #undef T