Lines Matching refs:jbt_reg_write_2
138 jbt_reg_write_2(struct td028ttec1_panel *lcd, in jbt_reg_write_2() function
187 jbt_reg_write_2(lcd, JBT_REG_OUTPUT_CONTROL, 0xfff9, &ret); in td028ttec1_prepare()
218 jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040, &ret); in td028ttec1_prepare()
219 jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0, &ret); in td028ttec1_prepare()
220 jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020, &ret); in td028ttec1_prepare()
221 jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0, &ret); in td028ttec1_prepare()
223 jbt_reg_write_2(lcd, JBT_REG_GAMMA1_FINE_1, 0x5533, &ret); in td028ttec1_prepare()
228 jbt_reg_write_2(lcd, JBT_REG_HCLOCK_VGA, 0x1f0, &ret); in td028ttec1_prepare()
230 jbt_reg_write_2(lcd, JBT_REG_BLANK_TH_TV, 0x0804, &ret); in td028ttec1_prepare()
233 jbt_reg_write_2(lcd, JBT_REG_CKV_1_2, 0x0000, &ret); in td028ttec1_prepare()
235 jbt_reg_write_2(lcd, JBT_REG_OEV_TIMING, 0x0d0e, &ret); in td028ttec1_prepare()
236 jbt_reg_write_2(lcd, JBT_REG_ASW_TIMING_1, 0x11a4, &ret); in td028ttec1_prepare()
262 jbt_reg_write_2(lcd, JBT_REG_OUTPUT_CONTROL, 0x8002, NULL); in td028ttec1_unprepare()