Lines Matching refs:dpm_table
410 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table() local
418 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
419 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
421 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; in ci_populate_bapm_parameters_in_dpm_table()
422 dpm_table->GpuTjMax = in ci_populate_bapm_parameters_in_dpm_table()
424 dpm_table->GpuTjHyst = 8; in ci_populate_bapm_parameters_in_dpm_table()
426 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base; in ci_populate_bapm_parameters_in_dpm_table()
429 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000); in ci_populate_bapm_parameters_in_dpm_table()
430 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256); in ci_populate_bapm_parameters_in_dpm_table()
432 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0); in ci_populate_bapm_parameters_in_dpm_table()
433 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0); in ci_populate_bapm_parameters_in_dpm_table()
436 dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient); in ci_populate_bapm_parameters_in_dpm_table()
443 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1); in ci_populate_bapm_parameters_in_dpm_table()
444 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2); in ci_populate_bapm_parameters_in_dpm_table()
2518 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { in ci_do_program_memory_timing_parameters()
2519 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { in ci_do_program_memory_timing_parameters()
2521 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()
2522 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()
2573 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table) in ci_get_dpm_level_enable_mask_value() argument
2578 for (i = dpm_table->count; i > 0; i--) { in ci_get_dpm_level_enable_mask_value()
2580 if (dpm_table->dpm_levels[i-1].enabled) in ci_get_dpm_level_enable_mask_value()
2593 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_smc_link_level() local
2596 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) { in ci_populate_smc_link_level()
2598 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value; in ci_populate_smc_link_level()
2600 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in ci_populate_smc_link_level()
2606 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; in ci_populate_smc_link_level()
2608 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in ci_populate_smc_link_level()
3242 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_graphic_levels() local
3252 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
3254 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
3261 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
3267 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
3269 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels()
3289 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_memory_levels() local
3299 for (i = 0; i < dpm_table->mclk_table.count; i++) { in ci_populate_all_memory_levels()
3300 if (dpm_table->mclk_table.dpm_levels[i].value == 0) in ci_populate_all_memory_levels()
3303 dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
3311 if ((dpm_table->mclk_table.count >= 2) && in ci_populate_all_memory_levels()
3321 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
3323 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in ci_populate_all_memory_levels()
3325 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = in ci_populate_all_memory_levels()
3338 struct ci_single_dpm_table* dpm_table, in ci_reset_single_dpm_table() argument
3343 dpm_table->count = count; in ci_reset_single_dpm_table()
3345 dpm_table->dpm_levels[i].enabled = false; in ci_reset_single_dpm_table()
3348 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table, in ci_setup_pcie_table_entry() argument
3351 dpm_table->dpm_levels[index].value = pcie_gen; in ci_setup_pcie_table_entry()
3352 dpm_table->dpm_levels[index].param1 = pcie_lanes; in ci_setup_pcie_table_entry()
3353 dpm_table->dpm_levels[index].enabled = true; in ci_setup_pcie_table_entry()
3372 &pi->dpm_table.pcie_speed_table, in ci_setup_default_pcie_tables()
3376 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3380 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3383 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1, in ci_setup_default_pcie_tables()
3386 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2, in ci_setup_default_pcie_tables()
3389 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3, in ci_setup_default_pcie_tables()
3392 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4, in ci_setup_default_pcie_tables()
3395 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5, in ci_setup_default_pcie_tables()
3399 pi->dpm_table.pcie_speed_table.count = 6; in ci_setup_default_pcie_tables()
3424 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table)); in ci_setup_default_dpm_tables()
3427 &pi->dpm_table.sclk_table, in ci_setup_default_dpm_tables()
3430 &pi->dpm_table.mclk_table, in ci_setup_default_dpm_tables()
3433 &pi->dpm_table.vddc_table, in ci_setup_default_dpm_tables()
3436 &pi->dpm_table.vddci_table, in ci_setup_default_dpm_tables()
3439 &pi->dpm_table.mvdd_table, in ci_setup_default_dpm_tables()
3442 pi->dpm_table.sclk_table.count = 0; in ci_setup_default_dpm_tables()
3445 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != in ci_setup_default_dpm_tables()
3447 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = in ci_setup_default_dpm_tables()
3449 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = in ci_setup_default_dpm_tables()
3451 pi->dpm_table.sclk_table.count++; in ci_setup_default_dpm_tables()
3455 pi->dpm_table.mclk_table.count = 0; in ci_setup_default_dpm_tables()
3458 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != in ci_setup_default_dpm_tables()
3460 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = in ci_setup_default_dpm_tables()
3462 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = in ci_setup_default_dpm_tables()
3464 pi->dpm_table.mclk_table.count++; in ci_setup_default_dpm_tables()
3469 pi->dpm_table.vddc_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3471 pi->dpm_table.vddc_table.dpm_levels[i].param1 = in ci_setup_default_dpm_tables()
3473 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3475 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; in ci_setup_default_dpm_tables()
3480 pi->dpm_table.vddci_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3482 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3484 pi->dpm_table.vddci_table.count = allowed_mclk_table->count; in ci_setup_default_dpm_tables()
3490 pi->dpm_table.mvdd_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3492 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3494 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count; in ci_setup_default_dpm_tables()
3592 ret = ci_find_boot_level(&pi->dpm_table.sclk_table, in ci_init_smc_table()
3596 ret = ci_find_boot_level(&pi->dpm_table.mclk_table, in ci_init_smc_table()
3629 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1; in ci_init_smc_table()
3667 struct ci_single_dpm_table *dpm_table, in ci_trim_single_dpm_states() argument
3672 for (i = 0; i < dpm_table->count; i++) { in ci_trim_single_dpm_states()
3673 if ((dpm_table->dpm_levels[i].value < low_limit) || in ci_trim_single_dpm_states()
3674 (dpm_table->dpm_levels[i].value > high_limit)) in ci_trim_single_dpm_states()
3675 dpm_table->dpm_levels[i].enabled = false; in ci_trim_single_dpm_states()
3677 dpm_table->dpm_levels[i].enabled = true; in ci_trim_single_dpm_states()
3686 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table; in ci_trim_pcie_dpm_states()
3728 &pi->dpm_table.sclk_table, in ci_trim_dpm_states()
3733 &pi->dpm_table.mclk_table, in ci_trim_dpm_states()
3823 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; in ci_find_dpm_states_clocks_in_dpm_table()
3825 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; in ci_find_dpm_states_clocks_in_dpm_table()
3867 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_and_upload_sclk_mclk_dpm_levels() local
3874 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk; in ci_populate_and_upload_sclk_mclk_dpm_levels()
3877 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk; in ci_populate_and_upload_sclk_mclk_dpm_levels()
4142 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table); in ci_generate_dpm_level_enable_mask()
4144 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table); in ci_generate_dpm_level_enable_mask()
4152 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table); in ci_generate_dpm_level_enable_mask()
4707 for (i = 0; i < pi->dpm_table.mclk_table.count; i++) in ci_convert_mc_reg_table_to_smc()
4709 pi->dpm_table.mclk_table.dpm_levels[i].value, in ci_convert_mc_reg_table_to_smc()
4748 pi->dpm_table.mclk_table.count, in ci_update_and_upload_mc_reg_table()
5640 SMU7_Discrete_DpmTable *dpm_table; in ci_dpm_init() local
5789 dpm_table = &pi->smc_state_table; in ci_dpm_init()
5793 dpm_table->VRHotGpio = gpio.shift; in ci_dpm_init()
5796 dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN; in ci_dpm_init()
5802 dpm_table->AcDcGpio = gpio.shift; in ci_dpm_init()
5805 dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN; in ci_dpm_init()