Lines Matching refs:ring
63 struct radeon_ring *ring) in cik_sdma_get_rptr() argument
68 rptr = rdev->wb.wb[ring->rptr_offs/4]; in cik_sdma_get_rptr()
70 if (ring->idx == R600_RING_TYPE_DMA_INDEX) in cik_sdma_get_rptr()
90 struct radeon_ring *ring) in cik_sdma_get_wptr() argument
94 if (ring->idx == R600_RING_TYPE_DMA_INDEX) in cik_sdma_get_wptr()
111 struct radeon_ring *ring) in cik_sdma_set_wptr() argument
115 if (ring->idx == R600_RING_TYPE_DMA_INDEX) in cik_sdma_set_wptr()
120 WREG32(reg, (ring->wptr << 2) & 0x3fffc); in cik_sdma_set_wptr()
135 struct radeon_ring *ring = &rdev->ring[ib->ring]; in cik_sdma_ring_ib_execute() local
136 u32 extra_bits = (ib->vm ? ib->vm->ids[ib->ring].id : 0) & 0xf; in cik_sdma_ring_ib_execute()
139 u32 next_rptr = ring->wptr + 5; in cik_sdma_ring_ib_execute()
143 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); in cik_sdma_ring_ib_execute()
144 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in cik_sdma_ring_ib_execute()
145 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); in cik_sdma_ring_ib_execute()
146 radeon_ring_write(ring, 1); /* number of DWs to follow */ in cik_sdma_ring_ib_execute()
147 radeon_ring_write(ring, next_rptr); in cik_sdma_ring_ib_execute()
151 while ((ring->wptr & 7) != 4) in cik_sdma_ring_ib_execute()
152 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); in cik_sdma_ring_ib_execute()
153 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); in cik_sdma_ring_ib_execute()
154 radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ in cik_sdma_ring_ib_execute()
155 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); in cik_sdma_ring_ib_execute()
156 radeon_ring_write(ring, ib->length_dw); in cik_sdma_ring_ib_execute()
171 struct radeon_ring *ring = &rdev->ring[ridx]; in cik_sdma_hdp_flush_ring_emit() local
181 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); in cik_sdma_hdp_flush_ring_emit()
182 radeon_ring_write(ring, GPU_HDP_FLUSH_DONE); in cik_sdma_hdp_flush_ring_emit()
183 radeon_ring_write(ring, GPU_HDP_FLUSH_REQ); in cik_sdma_hdp_flush_ring_emit()
184 radeon_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_hdp_flush_ring_emit()
185 radeon_ring_write(ring, ref_and_mask); /* mask */ in cik_sdma_hdp_flush_ring_emit()
186 radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ in cik_sdma_hdp_flush_ring_emit()
202 struct radeon_ring *ring = &rdev->ring[fence->ring]; in cik_sdma_fence_ring_emit() local
203 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cik_sdma_fence_ring_emit()
206 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); in cik_sdma_fence_ring_emit()
207 radeon_ring_write(ring, lower_32_bits(addr)); in cik_sdma_fence_ring_emit()
208 radeon_ring_write(ring, upper_32_bits(addr)); in cik_sdma_fence_ring_emit()
209 radeon_ring_write(ring, fence->seq); in cik_sdma_fence_ring_emit()
211 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); in cik_sdma_fence_ring_emit()
213 cik_sdma_hdp_flush_ring_emit(rdev, fence->ring); in cik_sdma_fence_ring_emit()
228 struct radeon_ring *ring, in cik_sdma_semaphore_ring_emit() argument
235 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits)); in cik_sdma_semaphore_ring_emit()
236 radeon_ring_write(ring, addr & 0xfffffff8); in cik_sdma_semaphore_ring_emit()
237 radeon_ring_write(ring, upper_32_bits(addr)); in cik_sdma_semaphore_ring_emit()
268 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false; in cik_sdma_gfx_stop()
269 rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false; in cik_sdma_gfx_stop()
366 struct radeon_ring *ring; in cik_sdma_gfx_resume() local
374 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in cik_sdma_gfx_resume()
378 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in cik_sdma_gfx_resume()
387 rb_bufsz = order_base_2(ring->ring_size / 4); in cik_sdma_gfx_resume()
407 WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8); in cik_sdma_gfx_resume()
408 WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40); in cik_sdma_gfx_resume()
410 ring->wptr = 0; in cik_sdma_gfx_resume()
411 WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2); in cik_sdma_gfx_resume()
423 ring->ready = true; in cik_sdma_gfx_resume()
425 r = radeon_ring_test(rdev, ring->idx, ring); in cik_sdma_gfx_resume()
427 ring->ready = false; in cik_sdma_gfx_resume()
560 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); in cik_sdma_fini()
561 radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]); in cik_sdma_fini()
586 struct radeon_ring *ring = &rdev->ring[ring_index]; in cik_copy_dma() local
595 r = radeon_ring_lock(rdev, ring, num_loops * 7 + 14); in cik_copy_dma()
603 radeon_sync_rings(rdev, &sync, ring->idx); in cik_copy_dma()
610 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0)); in cik_copy_dma()
611 radeon_ring_write(ring, cur_size_in_bytes); in cik_copy_dma()
612 radeon_ring_write(ring, 0); /* src/dst endian swap */ in cik_copy_dma()
613 radeon_ring_write(ring, lower_32_bits(src_offset)); in cik_copy_dma()
614 radeon_ring_write(ring, upper_32_bits(src_offset)); in cik_copy_dma()
615 radeon_ring_write(ring, lower_32_bits(dst_offset)); in cik_copy_dma()
616 radeon_ring_write(ring, upper_32_bits(dst_offset)); in cik_copy_dma()
621 r = radeon_fence_emit(rdev, &fence, ring->idx); in cik_copy_dma()
623 radeon_ring_unlock_undo(rdev, ring); in cik_copy_dma()
628 radeon_ring_unlock_commit(rdev, ring, false); in cik_copy_dma()
645 struct radeon_ring *ring) in cik_sdma_ring_test() argument
653 if (ring->idx == R600_RING_TYPE_DMA_INDEX) in cik_sdma_ring_test()
663 r = radeon_ring_lock(rdev, ring, 5); in cik_sdma_ring_test()
665 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r); in cik_sdma_ring_test()
668 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); in cik_sdma_ring_test()
669 radeon_ring_write(ring, lower_32_bits(gpu_addr)); in cik_sdma_ring_test()
670 radeon_ring_write(ring, upper_32_bits(gpu_addr)); in cik_sdma_ring_test()
671 radeon_ring_write(ring, 1); /* number of DWs to follow */ in cik_sdma_ring_test()
672 radeon_ring_write(ring, 0xDEADBEEF); in cik_sdma_ring_test()
673 radeon_ring_unlock_commit(rdev, ring, false); in cik_sdma_ring_test()
683 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); in cik_sdma_ring_test()
686 ring->idx, tmp); in cik_sdma_ring_test()
701 int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) in cik_sdma_ib_test() argument
710 if (ring->idx == R600_RING_TYPE_DMA_INDEX) in cik_sdma_ib_test()
720 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); in cik_sdma_ib_test()
756 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); in cik_sdma_ib_test()
774 bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) in cik_sdma_is_lockup() argument
779 if (ring->idx == R600_RING_TYPE_DMA_INDEX) in cik_sdma_is_lockup()
785 radeon_ring_lockup_update(rdev, ring); in cik_sdma_is_lockup()
788 return radeon_ring_test_lockup(rdev, ring); in cik_sdma_is_lockup()
944 void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, in cik_dma_vm_flush() argument
950 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); in cik_dma_vm_flush()
952 radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2); in cik_dma_vm_flush()
954 radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2); in cik_dma_vm_flush()
956 radeon_ring_write(ring, pd_addr >> 12); in cik_dma_vm_flush()
959 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); in cik_dma_vm_flush()
960 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); in cik_dma_vm_flush()
961 radeon_ring_write(ring, VMID(vm_id)); in cik_dma_vm_flush()
963 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); in cik_dma_vm_flush()
964 radeon_ring_write(ring, SH_MEM_BASES >> 2); in cik_dma_vm_flush()
965 radeon_ring_write(ring, 0); in cik_dma_vm_flush()
967 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); in cik_dma_vm_flush()
968 radeon_ring_write(ring, SH_MEM_CONFIG >> 2); in cik_dma_vm_flush()
969 radeon_ring_write(ring, 0); in cik_dma_vm_flush()
971 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); in cik_dma_vm_flush()
972 radeon_ring_write(ring, SH_MEM_APE1_BASE >> 2); in cik_dma_vm_flush()
973 radeon_ring_write(ring, 1); in cik_dma_vm_flush()
975 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); in cik_dma_vm_flush()
976 radeon_ring_write(ring, SH_MEM_APE1_LIMIT >> 2); in cik_dma_vm_flush()
977 radeon_ring_write(ring, 0); in cik_dma_vm_flush()
979 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); in cik_dma_vm_flush()
980 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); in cik_dma_vm_flush()
981 radeon_ring_write(ring, VMID(0)); in cik_dma_vm_flush()
984 cik_sdma_hdp_flush_ring_emit(rdev, ring->idx); in cik_dma_vm_flush()
987 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); in cik_dma_vm_flush()
988 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); in cik_dma_vm_flush()
989 radeon_ring_write(ring, 1 << vm_id); in cik_dma_vm_flush()
991 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); in cik_dma_vm_flush()
992 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); in cik_dma_vm_flush()
993 radeon_ring_write(ring, 0); in cik_dma_vm_flush()
994 radeon_ring_write(ring, 0); /* reference */ in cik_dma_vm_flush()
995 radeon_ring_write(ring, 0); /* mask */ in cik_dma_vm_flush()
996 radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ in cik_dma_vm_flush()