Lines Matching refs:reloc
1096 struct radeon_bo_list *reloc; in evergreen_cs_handle_reg() local
1142 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1148 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1171 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1179 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1180 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1181 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()
1184 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg()
1213 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1220 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1221 track->db_z_read_bo = reloc->robj; in evergreen_cs_handle_reg()
1225 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1232 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1233 track->db_z_write_bo = reloc->robj; in evergreen_cs_handle_reg()
1237 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1244 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1245 track->db_s_read_bo = reloc->robj; in evergreen_cs_handle_reg()
1249 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1256 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1257 track->db_s_write_bo = reloc->robj; in evergreen_cs_handle_reg()
1272 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1280 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1281 track->vgt_strmout_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1294 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1300 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1359 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1365 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1366 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1377 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1383 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1384 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1438 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1445 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()
1448 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg()
1466 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1473 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()
1476 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg()
1499 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1504 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1505 track->cb_color_fmask_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1516 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1521 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1522 track->cb_color_cmask_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1554 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1562 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1563 track->cb_color_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1570 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1578 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1579 track->cb_color_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1583 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1590 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1591 track->htile_bo = reloc->robj; in evergreen_cs_handle_reg()
1701 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1707 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1715 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1721 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1729 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1735 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1774 struct radeon_bo_list *reloc; in evergreen_packet3_check() local
1812 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
1818 offset = reloc->gpu_offset + in evergreen_packet3_check()
1858 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
1864 offset = reloc->gpu_offset + in evergreen_packet3_check()
1893 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
1899 offset = reloc->gpu_offset + in evergreen_packet3_check()
1921 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
1927 offset = reloc->gpu_offset + in evergreen_packet3_check()
2016 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2022 track->indirect_draw_buffer_size = radeon_bo_size(reloc->robj); in evergreen_packet3_check()
2024 ib[idx+1] = reloc->gpu_offset; in evergreen_packet3_check()
2025 ib[idx+2] = upper_32_bits(reloc->gpu_offset) & 0xff; in evergreen_packet3_check()
2073 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2078 ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff); in evergreen_packet3_check()
2094 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2100 offset = reloc->gpu_offset + in evergreen_packet3_check()
2148 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2157 offset = reloc->gpu_offset + tmp; in evergreen_packet3_check()
2159 if ((tmp + size) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2161 tmp + size, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2186 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2195 offset = reloc->gpu_offset + tmp; in evergreen_packet3_check()
2197 if ((tmp + size) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2199 tmp + size, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2226 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2231 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_packet3_check()
2242 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2247 offset = reloc->gpu_offset + in evergreen_packet3_check()
2263 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2269 offset = reloc->gpu_offset + in evergreen_packet3_check()
2285 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2291 offset = reloc->gpu_offset + in evergreen_packet3_check()
2354 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2361 TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_packet3_check()
2362 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_packet3_check()
2365 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_packet3_check()
2376 texture = reloc->robj; in evergreen_packet3_check()
2377 toffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_packet3_check()
2391 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2396 moffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_packet3_check()
2397 mipmap = reloc->robj; in evergreen_packet3_check()
2410 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2417 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2420 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset; in evergreen_packet3_check()
2423 offset64 = reloc->gpu_offset + offset; in evergreen_packet3_check()
2492 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2499 if ((offset + 4) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2501 offset + 4, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2504 offset += reloc->gpu_offset; in evergreen_packet3_check()
2511 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2518 if ((offset + 4) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2520 offset + 4, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2523 offset += reloc->gpu_offset; in evergreen_packet3_check()
2536 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2547 if ((offset + 8) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2549 offset + 8, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2552 offset += reloc->gpu_offset; in evergreen_packet3_check()
2565 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2572 if ((offset + 4) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2574 offset + 4, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2577 offset += reloc->gpu_offset; in evergreen_packet3_check()
2592 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2599 if ((offset + 4) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2601 offset + 4, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2604 offset += reloc->gpu_offset; in evergreen_packet3_check()
2642 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2653 offset += reloc->gpu_offset; in evergreen_packet3_check()