Lines Matching refs:gb_addr_config
880 u32 gb_addr_config = 0; in cayman_gpu_init() local
913 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN; in cayman_gpu_init()
987 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN; in cayman_gpu_init()
1018 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT; in cayman_gpu_init()
1020 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT; in cayman_gpu_init()
1022 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT; in cayman_gpu_init()
1024 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT; in cayman_gpu_init()
1026 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT; in cayman_gpu_init()
1028 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT; in cayman_gpu_init()
1074 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; in cayman_gpu_init()
1076 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; in cayman_gpu_init()
1114 WREG32(GB_ADDR_CONFIG, gb_addr_config); in cayman_gpu_init()
1115 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); in cayman_gpu_init()
1117 WREG32(DMIF_ADDR_CALC, gb_addr_config); in cayman_gpu_init()
1118 WREG32(HDP_ADDR_CONFIG, gb_addr_config); in cayman_gpu_init()
1119 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); in cayman_gpu_init()
1120 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); in cayman_gpu_init()
1121 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); in cayman_gpu_init()
1122 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); in cayman_gpu_init()
1123 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); in cayman_gpu_init()
1135 tmp = gb_addr_config & NUM_PIPES_MASK; in cayman_gpu_init()