Lines Matching refs:rps
733 struct ni_ps *ni_get_ps(struct radeon_ps *rps) in ni_get_ps() argument
735 struct ni_ps *ps = rps->ps_priv; in ni_get_ps()
786 struct radeon_ps *rps) in ni_apply_state_adjust_rules() argument
788 struct ni_ps *ps = ni_get_ps(rps); in ni_apply_state_adjust_rules()
3563 struct radeon_ps *rps) in ni_update_current_ps() argument
3565 struct ni_ps *new_ps = ni_get_ps(rps); in ni_update_current_ps()
3569 eg_pi->current_rps = *rps; in ni_update_current_ps()
3575 struct radeon_ps *rps) in ni_update_requested_ps() argument
3577 struct ni_ps *new_ps = ni_get_ps(rps); in ni_update_requested_ps()
3581 eg_pi->requested_rps = *rps; in ni_update_requested_ps()
3896 struct radeon_ps *rps, in ni_parse_pplib_non_clock_info() argument
3900 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); in ni_parse_pplib_non_clock_info()
3901 rps->class = le16_to_cpu(non_clock_info->usClassification); in ni_parse_pplib_non_clock_info()
3902 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); in ni_parse_pplib_non_clock_info()
3905 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in ni_parse_pplib_non_clock_info()
3906 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in ni_parse_pplib_non_clock_info()
3907 } else if (r600_is_uvd_state(rps->class, rps->class2)) { in ni_parse_pplib_non_clock_info()
3908 rps->vclk = RV770_DEFAULT_VCLK_FREQ; in ni_parse_pplib_non_clock_info()
3909 rps->dclk = RV770_DEFAULT_DCLK_FREQ; in ni_parse_pplib_non_clock_info()
3911 rps->vclk = 0; in ni_parse_pplib_non_clock_info()
3912 rps->dclk = 0; in ni_parse_pplib_non_clock_info()
3915 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) in ni_parse_pplib_non_clock_info()
3916 rdev->pm.dpm.boot_ps = rps; in ni_parse_pplib_non_clock_info()
3917 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) in ni_parse_pplib_non_clock_info()
3918 rdev->pm.dpm.uvd_ps = rps; in ni_parse_pplib_non_clock_info()
3922 struct radeon_ps *rps, int index, in ni_parse_pplib_clock_info() argument
3927 struct ni_ps *ps = ni_get_ps(rps); in ni_parse_pplib_clock_info()
3947 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { in ni_parse_pplib_clock_info()
3956 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) { in ni_parse_pplib_clock_info()
3968 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { in ni_parse_pplib_clock_info()
3977 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == in ni_parse_pplib_clock_info()
4284 struct radeon_ps *rps) in ni_dpm_print_power_state() argument
4286 struct ni_ps *ps = ni_get_ps(rps); in ni_dpm_print_power_state()
4290 r600_dpm_print_class_info(rps->class, rps->class2); in ni_dpm_print_power_state()
4291 r600_dpm_print_cap_info(rps->caps); in ni_dpm_print_power_state()
4292 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in ni_dpm_print_power_state()
4302 r600_dpm_print_ps_status(rdev, rps); in ni_dpm_print_power_state()
4309 struct radeon_ps *rps = &eg_pi->current_rps; in ni_dpm_debugfs_print_current_performance_level() local
4310 struct ni_ps *ps = ni_get_ps(rps); in ni_dpm_debugfs_print_current_performance_level()
4320 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in ni_dpm_debugfs_print_current_performance_level()
4329 struct radeon_ps *rps = &eg_pi->current_rps; in ni_dpm_get_current_sclk() local
4330 struct ni_ps *ps = ni_get_ps(rps); in ni_dpm_get_current_sclk()
4347 struct radeon_ps *rps = &eg_pi->current_rps; in ni_dpm_get_current_mclk() local
4348 struct ni_ps *ps = ni_get_ps(rps); in ni_dpm_get_current_mclk()