Lines Matching refs:reset_mask
1617 u32 reset_mask = 0; in r600_gpu_check_soft_reset() local
1628 reset_mask |= RADEON_RESET_GFX; in r600_gpu_check_soft_reset()
1635 reset_mask |= RADEON_RESET_GFX; in r600_gpu_check_soft_reset()
1640 reset_mask |= RADEON_RESET_CP; in r600_gpu_check_soft_reset()
1643 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; in r600_gpu_check_soft_reset()
1648 reset_mask |= RADEON_RESET_DMA; in r600_gpu_check_soft_reset()
1653 reset_mask |= RADEON_RESET_RLC; in r600_gpu_check_soft_reset()
1656 reset_mask |= RADEON_RESET_IH; in r600_gpu_check_soft_reset()
1659 reset_mask |= RADEON_RESET_SEM; in r600_gpu_check_soft_reset()
1662 reset_mask |= RADEON_RESET_GRBM; in r600_gpu_check_soft_reset()
1665 reset_mask |= RADEON_RESET_VMC; in r600_gpu_check_soft_reset()
1670 reset_mask |= RADEON_RESET_MC; in r600_gpu_check_soft_reset()
1673 reset_mask |= RADEON_RESET_DISPLAY; in r600_gpu_check_soft_reset()
1676 if (reset_mask & RADEON_RESET_MC) { in r600_gpu_check_soft_reset()
1677 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); in r600_gpu_check_soft_reset()
1678 reset_mask &= ~RADEON_RESET_MC; in r600_gpu_check_soft_reset()
1681 return reset_mask; in r600_gpu_check_soft_reset()
1684 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) in r600_gpu_soft_reset() argument
1690 if (reset_mask == 0) in r600_gpu_soft_reset()
1693 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); in r600_gpu_soft_reset()
1706 if (reset_mask & RADEON_RESET_DMA) { in r600_gpu_soft_reset()
1720 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { in r600_gpu_soft_reset()
1749 if (reset_mask & RADEON_RESET_CP) { in r600_gpu_soft_reset()
1756 if (reset_mask & RADEON_RESET_DMA) { in r600_gpu_soft_reset()
1763 if (reset_mask & RADEON_RESET_RLC) in r600_gpu_soft_reset()
1766 if (reset_mask & RADEON_RESET_SEM) in r600_gpu_soft_reset()
1769 if (reset_mask & RADEON_RESET_IH) in r600_gpu_soft_reset()
1772 if (reset_mask & RADEON_RESET_GRBM) in r600_gpu_soft_reset()
1776 if (reset_mask & RADEON_RESET_MC) in r600_gpu_soft_reset()
1780 if (reset_mask & RADEON_RESET_VMC) in r600_gpu_soft_reset()
1883 u32 reset_mask; in r600_asic_reset() local
1890 reset_mask = r600_gpu_check_soft_reset(rdev); in r600_asic_reset()
1892 if (reset_mask) in r600_asic_reset()
1896 r600_gpu_soft_reset(rdev, reset_mask); in r600_asic_reset()
1898 reset_mask = r600_gpu_check_soft_reset(rdev); in r600_asic_reset()
1901 if (reset_mask && radeon_hard_reset) in r600_asic_reset()
1904 reset_mask = r600_gpu_check_soft_reset(rdev); in r600_asic_reset()
1906 if (!reset_mask) in r600_asic_reset()
1923 u32 reset_mask = r600_gpu_check_soft_reset(rdev); in r600_gfx_is_lockup() local
1925 if (!(reset_mask & (RADEON_RESET_GFX | in r600_gfx_is_lockup()