Lines Matching refs:reloc
971 struct radeon_bo_list *reloc; in r600_cs_check_reg() local
1016 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in r600_cs_check_reg()
1022 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1034 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_cs_check_reg()
1043 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1076 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_cs_check_reg()
1084 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1085 track->vgt_strmout_bo[tmp] = reloc->robj; in r600_cs_check_reg()
1086 track->vgt_strmout_bo_mc[tmp] = reloc->gpu_offset; in r600_cs_check_reg()
1099 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_cs_check_reg()
1105 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1135 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_cs_check_reg()
1142 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1145 } else if (reloc->tiling_flags & RADEON_TILING_MICRO) { in r600_cs_check_reg()
1207 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_cs_check_reg()
1212 track->cb_color_frag_bo[tmp] = reloc->robj; in r600_cs_check_reg()
1214 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1238 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_cs_check_reg()
1243 track->cb_color_tile_bo[tmp] = reloc->robj; in r600_cs_check_reg()
1245 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1273 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_cs_check_reg()
1281 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1283 track->cb_color_bo[tmp] = reloc->robj; in r600_cs_check_reg()
1284 track->cb_color_bo_mc[tmp] = reloc->gpu_offset; in r600_cs_check_reg()
1288 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_cs_check_reg()
1295 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1296 track->db_bo = reloc->robj; in r600_cs_check_reg()
1297 track->db_bo_mc = reloc->gpu_offset; in r600_cs_check_reg()
1301 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_cs_check_reg()
1308 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1309 track->htile_bo = reloc->robj; in r600_cs_check_reg()
1371 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_cs_check_reg()
1377 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1380 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_cs_check_reg()
1386 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1631 struct radeon_bo_list *reloc; in r600_packet3_check() local
1669 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
1675 offset = reloc->gpu_offset + in r600_packet3_check()
1710 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
1716 offset = reloc->gpu_offset + in r600_packet3_check()
1762 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
1768 offset = reloc->gpu_offset + in r600_packet3_check()
1799 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
1808 offset = reloc->gpu_offset + tmp; in r600_packet3_check()
1810 if ((tmp + size) > radeon_bo_size(reloc->robj)) { in r600_packet3_check()
1812 tmp + size, radeon_bo_size(reloc->robj)); in r600_packet3_check()
1829 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
1838 offset = reloc->gpu_offset + tmp; in r600_packet3_check()
1840 if ((tmp + size) > radeon_bo_size(reloc->robj)) { in r600_packet3_check()
1842 tmp + size, radeon_bo_size(reloc->robj)); in r600_packet3_check()
1859 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
1864 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_packet3_check()
1875 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
1880 offset = reloc->gpu_offset + in r600_packet3_check()
1896 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
1902 offset = reloc->gpu_offset + in r600_packet3_check()
1962 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
1967 base_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_packet3_check()
1969 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r600_packet3_check()
1971 else if (reloc->tiling_flags & RADEON_TILING_MICRO) in r600_packet3_check()
1974 texture = reloc->robj; in r600_packet3_check()
1976 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
1981 mip_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_packet3_check()
1982 mipmap = reloc->robj; in r600_packet3_check()
1987 reloc->tiling_flags); in r600_packet3_check()
1997 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
2004 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) { in r600_packet3_check()
2007 size + offset, radeon_bo_size(reloc->robj)); in r600_packet3_check()
2008 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset; in r600_packet3_check()
2011 offset64 = reloc->gpu_offset + offset; in r600_packet3_check()
2098 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
2104 if (reloc->robj != track->vgt_strmout_bo[idx_value]) { in r600_packet3_check()
2116 if ((offset + 4) > radeon_bo_size(reloc->robj)) { in r600_packet3_check()
2118 offset + 4, radeon_bo_size(reloc->robj)); in r600_packet3_check()
2121 ib[idx+1] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_packet3_check()
2142 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
2149 if ((offset + 4) > radeon_bo_size(reloc->robj)) { in r600_packet3_check()
2151 offset + 4, radeon_bo_size(reloc->robj)); in r600_packet3_check()
2154 offset += reloc->gpu_offset; in r600_packet3_check()
2161 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
2168 if ((offset + 4) > radeon_bo_size(reloc->robj)) { in r600_packet3_check()
2170 offset + 4, radeon_bo_size(reloc->robj)); in r600_packet3_check()
2173 offset += reloc->gpu_offset; in r600_packet3_check()
2186 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
2197 if ((offset + 8) > radeon_bo_size(reloc->robj)) { in r600_packet3_check()
2199 offset + 8, radeon_bo_size(reloc->robj)); in r600_packet3_check()
2202 offset += reloc->gpu_offset; in r600_packet3_check()
2215 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
2222 if ((offset + 4) > radeon_bo_size(reloc->robj)) { in r600_packet3_check()
2224 offset + 4, radeon_bo_size(reloc->robj)); in r600_packet3_check()
2227 offset += reloc->gpu_offset; in r600_packet3_check()
2239 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
2246 if ((offset + 4) > radeon_bo_size(reloc->robj)) { in r600_packet3_check()
2248 offset + 4, radeon_bo_size(reloc->robj)); in r600_packet3_check()
2251 offset += reloc->gpu_offset; in r600_packet3_check()