Lines Matching refs:DRM_DEBUG
33 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes)); in radeon_ucode_print_common_hdr()
34 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes)); in radeon_ucode_print_common_hdr()
35 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major)); in radeon_ucode_print_common_hdr()
36 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor)); in radeon_ucode_print_common_hdr()
37 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major)); in radeon_ucode_print_common_hdr()
38 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor)); in radeon_ucode_print_common_hdr()
39 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version)); in radeon_ucode_print_common_hdr()
40 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes)); in radeon_ucode_print_common_hdr()
41 DRM_DEBUG("ucode_array_offset_bytes: %u\n", in radeon_ucode_print_common_hdr()
43 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32)); in radeon_ucode_print_common_hdr()
51 DRM_DEBUG("MC\n"); in radeon_ucode_print_mc_hdr()
58 DRM_DEBUG("io_debug_size_bytes: %u\n", in radeon_ucode_print_mc_hdr()
60 DRM_DEBUG("io_debug_array_offset_bytes: %u\n", in radeon_ucode_print_mc_hdr()
72 DRM_DEBUG("SMC\n"); in radeon_ucode_print_smc_hdr()
79 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(smc_hdr->ucode_start_addr)); in radeon_ucode_print_smc_hdr()
90 DRM_DEBUG("GFX\n"); in radeon_ucode_print_gfx_hdr()
97 DRM_DEBUG("ucode_feature_version: %u\n", in radeon_ucode_print_gfx_hdr()
99 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset)); in radeon_ucode_print_gfx_hdr()
100 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size)); in radeon_ucode_print_gfx_hdr()
111 DRM_DEBUG("RLC\n"); in radeon_ucode_print_rlc_hdr()
118 DRM_DEBUG("ucode_feature_version: %u\n", in radeon_ucode_print_rlc_hdr()
120 DRM_DEBUG("save_and_restore_offset: %u\n", in radeon_ucode_print_rlc_hdr()
122 DRM_DEBUG("clear_state_descriptor_offset: %u\n", in radeon_ucode_print_rlc_hdr()
124 DRM_DEBUG("avail_scratch_ram_locations: %u\n", in radeon_ucode_print_rlc_hdr()
126 DRM_DEBUG("master_pkt_description_offset: %u\n", in radeon_ucode_print_rlc_hdr()
138 DRM_DEBUG("SDMA\n"); in radeon_ucode_print_sdma_hdr()
145 DRM_DEBUG("ucode_feature_version: %u\n", in radeon_ucode_print_sdma_hdr()
147 DRM_DEBUG("ucode_change_version: %u\n", in radeon_ucode_print_sdma_hdr()
149 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset)); in radeon_ucode_print_sdma_hdr()
150 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size)); in radeon_ucode_print_sdma_hdr()