Lines Matching refs:vddc
1753 s64 kt, kv, leakage_w, i_leakage, vddc; in si_calculate_leakage_for_v_and_t_formula() local
1758 vddc = div64_s64(drm_int2fixp(v), 1000); in si_calculate_leakage_for_v_and_t_formula()
1767 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; in si_calculate_leakage_for_v_and_t_formula()
1770 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); in si_calculate_leakage_for_v_and_t_formula()
1772 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); in si_calculate_leakage_for_v_and_t_formula()
1791 s64 kt, kv, leakage_w, i_leakage, vddc; in si_calculate_leakage_for_v_formula() local
1794 vddc = div64_s64(drm_int2fixp(v), 1000); in si_calculate_leakage_for_v_formula()
1798 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); in si_calculate_leakage_for_v_formula()
1800 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); in si_calculate_leakage_for_v_formula()
2273 SISLANDS_SMC_VOLTAGE_VALUE vddc; in si_populate_power_containment_values() local
2330 state->performance_levels[i-1].vddc, &vddc); in si_populate_power_containment_values()
2334 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); in si_populate_power_containment_values()
2339 state->performance_levels[i].vddc, &vddc); in si_populate_power_containment_values()
2343 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); in si_populate_power_containment_values()
2529 if (table->entries[i].vddc > *max) in si_get_cac_std_voltage_max_min()
2530 *max = table->entries[i].vddc; in si_get_cac_std_voltage_max_min()
2531 if (table->entries[i].vddc < *min) in si_get_cac_std_voltage_max_min()
2532 *min = table->entries[i].vddc; in si_get_cac_std_voltage_max_min()
2954 u16 vddc, vddci, min_vce_voltage = 0; in si_apply_state_adjust_rules() local
3012 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) in si_apply_state_adjust_rules()
3013 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; in si_apply_state_adjust_rules()
3021 if (ps->performance_levels[i].vddc > max_limits->vddc) in si_apply_state_adjust_rules()
3022 ps->performance_levels[i].vddc = max_limits->vddc; in si_apply_state_adjust_rules()
3071 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; in si_apply_state_adjust_rules()
3074 vddc = ps->performance_levels[0].vddc; in si_apply_state_adjust_rules()
3087 ps->performance_levels[0].vddc = vddc; in si_apply_state_adjust_rules()
3098 ps->performance_levels[i].vddc = vddc; in si_apply_state_adjust_rules()
3104 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) in si_apply_state_adjust_rules()
3105 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; in si_apply_state_adjust_rules()
3133 if (ps->performance_levels[i].vddc < min_vce_voltage) in si_apply_state_adjust_rules()
3134 ps->performance_levels[i].vddc = min_vce_voltage; in si_apply_state_adjust_rules()
3137 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3143 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3146 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3151 max_limits->vddc, max_limits->vddci, in si_apply_state_adjust_rules()
3152 &ps->performance_levels[i].vddc, in si_apply_state_adjust_rules()
3158 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) in si_apply_state_adjust_rules()
3216 u16 vddc, count = 0; in si_get_leakage_vddc() local
3220 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); in si_get_leakage_vddc()
3222 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { in si_get_leakage_vddc()
3223 si_pi->leakage_voltage.entries[count].voltage = vddc; in si_get_leakage_vddc()
4146 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4149 …>pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; in si_get_std_voltage_value()
4161 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4164 …>pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; in si_get_std_voltage_value()
4171 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; in si_get_std_voltage_value()
4400 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4401 &table->initialState.level.vddc); in si_populate_smc_initial_state()
4407 &table->initialState.level.vddc, in si_populate_smc_initial_state()
4411 table->initialState.level.vddc.index, in si_populate_smc_initial_state()
4424 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4427 &table->initialState.level.vddc); in si_populate_smc_initial_state()
4494 pi->acpi_vddc, &table->ACPIState.level.vddc); in si_populate_smc_acpi_state()
4499 &table->ACPIState.level.vddc, &std_vddc); in si_populate_smc_acpi_state()
4502 table->ACPIState.level.vddc.index, in si_populate_smc_acpi_state()
4513 &table->ACPIState.level.vddc); in si_populate_smc_acpi_state()
4517 pi->min_vddc_in_table, &table->ACPIState.level.vddc); in si_populate_smc_acpi_state()
4522 &table->ACPIState.level.vddc, &std_vddc); in si_populate_smc_acpi_state()
4526 table->ACPIState.level.vddc.index, in si_populate_smc_acpi_state()
4540 &table->ACPIState.level.vddc); in si_populate_smc_acpi_state()
4631 state->level.std_vddc = state->level.vddc; in si_populate_ulv_state()
4740 if (ulv->supported && ulv->pl.vddc) { in si_init_smc_table()
5028 pl->vddc, &level->vddc); in si_convert_power_level_to_smc()
5033 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); in si_convert_power_level_to_smc()
5038 level->vddc.index, &level->std_vddc); in si_convert_power_level_to_smc()
5052 pl->vddc, in si_convert_power_level_to_smc()
5055 &level->vddc); in si_convert_power_level_to_smc()
5144 if (ulv->pl.vddc < in si_is_state_ulv_compatible()
5280 if (ulv->supported && ulv->pl.vddc) { in si_upload_ulv_state()
5653 if (ulv->supported && ulv->pl.vddc != 0) in si_populate_mc_reg_table()
6731 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); in si_parse_pplib_clock_info()
6740 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, in si_parse_pplib_clock_info()
6743 pl->vddc = leakage_voltage; in si_parse_pplib_clock_info()
6746 pi->acpi_vddc = pl->vddc; in si_parse_pplib_clock_info()
6762 if (pi->min_vddc_in_table > pl->vddc) in si_parse_pplib_clock_info()
6763 pi->min_vddc_in_table = pl->vddc; in si_parse_pplib_clock_info()
6765 if (pi->max_vddc_in_table < pl->vddc) in si_parse_pplib_clock_info()
6766 pi->max_vddc_in_table = pl->vddc; in si_parse_pplib_clock_info()
6770 u16 vddc, vddci, mvdd; in si_parse_pplib_clock_info() local
6771 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); in si_parse_pplib_clock_info()
6774 pl->vddc = vddc; in si_parse_pplib_clock_info()
6783 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; in si_parse_pplib_clock_info()
7089 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); in si_dpm_debugfs_print_current_performance_level()