Lines Matching refs:dc
44 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) in tegra_dc_readl_active() argument
48 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
49 value = tegra_dc_readl(dc, offset); in tegra_dc_readl_active()
50 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
73 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); in tegra_plane_offset()
81 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); in tegra_plane_readl()
87 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); in tegra_plane_writel()
90 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev) in tegra_dc_has_output() argument
92 struct device_node *np = dc->dev->of_node; in tegra_dc_has_output()
115 void tegra_dc_commit(struct tegra_dc *dc) in tegra_dc_commit() argument
117 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
118 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
311 struct tegra_dc *dc = plane->dc; in tegra_plane_use_horizontal_filtering() local
316 if (plane->index == 0 && dc->soc->has_win_a_without_filters) in tegra_plane_use_horizontal_filtering()
326 struct tegra_dc *dc = plane->dc; in tegra_plane_use_vertical_filtering() local
331 if (plane->index == 0 && dc->soc->has_win_a_without_filters) in tegra_plane_use_vertical_filtering()
334 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter) in tegra_plane_use_vertical_filtering()
344 struct tegra_dc *dc = plane->dc; in tegra_dc_setup_window() local
417 if (dc->soc->supports_block_linear) { in tegra_dc_setup_window()
523 if (dc->soc->has_legacy_blending) in tegra_dc_setup_window()
619 struct tegra_dc *dc = to_tegra_dc(new_plane_state->crtc); in tegra_plane_atomic_check() local
643 if (dc->soc->has_legacy_blending) { in tegra_plane_atomic_check()
654 !dc->soc->supports_block_linear) { in tegra_plane_atomic_check()
794 struct tegra_dc *dc) in tegra_primary_plane_create() argument
811 plane->dc = dc; in tegra_primary_plane_create()
813 num_formats = dc->soc->num_primary_formats; in tegra_primary_plane_create()
814 formats = dc->soc->primary_formats; in tegra_primary_plane_create()
815 modifiers = dc->soc->modifiers; in tegra_primary_plane_create()
841 dev_err(dc->dev, "failed to create rotation property: %d\n", in tegra_primary_plane_create()
899 struct tegra_dc *dc = to_tegra_dc(new_state->crtc); in tegra_cursor_atomic_update() local
902 u64 dma_mask = *dc->dev->dma_mask; in tegra_cursor_atomic_update()
915 if (!dc->soc->has_nvdisplay) in tegra_cursor_atomic_update()
942 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); in tegra_cursor_atomic_update()
946 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); in tegra_cursor_atomic_update()
950 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_update()
952 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_update()
954 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); in tegra_cursor_atomic_update()
958 if (dc->soc->has_nvdisplay) in tegra_cursor_atomic_update()
966 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); in tegra_cursor_atomic_update()
969 if (dc->soc->has_nvdisplay) { in tegra_cursor_atomic_update()
978 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR); in tegra_cursor_atomic_update()
982 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR); in tegra_cursor_atomic_update()
990 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); in tegra_cursor_atomic_update()
998 struct tegra_dc *dc; in tegra_cursor_atomic_disable() local
1005 dc = to_tegra_dc(old_state->crtc); in tegra_cursor_atomic_disable()
1007 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_disable()
1009 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_disable()
1026 struct tegra_dc *dc) in tegra_dc_cursor_plane_create() argument
1046 plane->dc = dc; in tegra_dc_cursor_plane_create()
1048 if (!dc->soc->has_nvdisplay) { in tegra_dc_cursor_plane_create()
1154 struct tegra_dc *dc, in tegra_dc_overlay_plane_create() argument
1171 plane->dc = dc; in tegra_dc_overlay_plane_create()
1173 num_formats = dc->soc->num_overlay_formats; in tegra_dc_overlay_plane_create()
1174 formats = dc->soc->overlay_formats; in tegra_dc_overlay_plane_create()
1206 dev_err(dc->dev, "failed to create rotation property: %d\n", in tegra_dc_overlay_plane_create()
1213 struct tegra_dc *dc) in tegra_dc_add_shared_planes() argument
1218 for (i = 0; i < dc->soc->num_wgrps; i++) { in tegra_dc_add_shared_planes()
1219 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; in tegra_dc_add_shared_planes()
1221 if (wgrp->dc == dc->pipe) { in tegra_dc_add_shared_planes()
1225 plane = tegra_shared_plane_create(drm, dc, in tegra_dc_add_shared_planes()
1247 struct tegra_dc *dc) in tegra_dc_add_planes() argument
1254 primary = tegra_primary_plane_create(drm, dc); in tegra_dc_add_planes()
1258 if (dc->soc->supports_cursor) in tegra_dc_add_planes()
1264 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i, in tegra_dc_add_planes()
1541 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_regs() local
1545 drm_modeset_lock(&dc->base.mutex, NULL); in tegra_dc_show_regs()
1547 if (!dc->base.state->active) { in tegra_dc_show_regs()
1556 offset, tegra_dc_readl(dc, offset)); in tegra_dc_show_regs()
1560 drm_modeset_unlock(&dc->base.mutex); in tegra_dc_show_regs()
1567 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_crc() local
1571 drm_modeset_lock(&dc->base.mutex, NULL); in tegra_dc_show_crc()
1573 if (!dc->base.state->active) { in tegra_dc_show_crc()
1579 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL); in tegra_dc_show_crc()
1580 tegra_dc_commit(dc); in tegra_dc_show_crc()
1582 drm_crtc_wait_one_vblank(&dc->base); in tegra_dc_show_crc()
1583 drm_crtc_wait_one_vblank(&dc->base); in tegra_dc_show_crc()
1585 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM); in tegra_dc_show_crc()
1588 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL); in tegra_dc_show_crc()
1591 drm_modeset_unlock(&dc->base.mutex); in tegra_dc_show_crc()
1598 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_stats() local
1600 seq_printf(s, "frames: %lu\n", dc->stats.frames); in tegra_dc_show_stats()
1601 seq_printf(s, "vblank: %lu\n", dc->stats.vblank); in tegra_dc_show_stats()
1602 seq_printf(s, "underflow: %lu\n", dc->stats.underflow); in tegra_dc_show_stats()
1603 seq_printf(s, "overflow: %lu\n", dc->stats.overflow); in tegra_dc_show_stats()
1605 seq_printf(s, "frames total: %lu\n", dc->stats.frames_total); in tegra_dc_show_stats()
1606 seq_printf(s, "vblank total: %lu\n", dc->stats.vblank_total); in tegra_dc_show_stats()
1607 seq_printf(s, "underflow total: %lu\n", dc->stats.underflow_total); in tegra_dc_show_stats()
1608 seq_printf(s, "overflow total: %lu\n", dc->stats.overflow_total); in tegra_dc_show_stats()
1624 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_late_register() local
1632 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), in tegra_dc_late_register()
1634 if (!dc->debugfs_files) in tegra_dc_late_register()
1638 dc->debugfs_files[i].data = dc; in tegra_dc_late_register()
1640 drm_debugfs_create_files(dc->debugfs_files, count, root, minor); in tegra_dc_late_register()
1649 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_early_unregister() local
1651 drm_debugfs_remove_files(dc->debugfs_files, count, minor); in tegra_dc_early_unregister()
1652 kfree(dc->debugfs_files); in tegra_dc_early_unregister()
1653 dc->debugfs_files = NULL; in tegra_dc_early_unregister()
1658 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_get_vblank_counter() local
1661 if (dc->syncpt && !dc->soc->has_nvdisplay) in tegra_dc_get_vblank_counter()
1662 return host1x_syncpt_read(dc->syncpt); in tegra_dc_get_vblank_counter()
1665 return (u32)drm_crtc_vblank_count(&dc->base); in tegra_dc_get_vblank_counter()
1670 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_enable_vblank() local
1673 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
1675 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
1682 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_disable_vblank() local
1685 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
1687 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
1704 static int tegra_dc_set_timings(struct tegra_dc *dc, in tegra_dc_set_timings() argument
1711 if (!dc->soc->has_nvdisplay) { in tegra_dc_set_timings()
1712 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); in tegra_dc_set_timings()
1715 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); in tegra_dc_set_timings()
1720 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); in tegra_dc_set_timings()
1724 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); in tegra_dc_set_timings()
1728 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); in tegra_dc_set_timings()
1731 tegra_dc_writel(dc, value, DC_DISP_ACTIVE); in tegra_dc_set_timings()
1748 int tegra_dc_state_setup_clock(struct tegra_dc *dc, in tegra_dc_state_setup_clock() argument
1755 if (!clk_has_parent(dc->clk, clk)) in tegra_dc_state_setup_clock()
1765 static void tegra_dc_commit_state(struct tegra_dc *dc, in tegra_dc_commit_state() argument
1771 err = clk_set_parent(dc->clk, state->clk); in tegra_dc_commit_state()
1773 dev_err(dc->dev, "failed to set parent clock: %d\n", err); in tegra_dc_commit_state()
1786 dev_err(dc->dev, in tegra_dc_commit_state()
1790 err = clk_set_rate(dc->clk, state->pclk); in tegra_dc_commit_state()
1792 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n", in tegra_dc_commit_state()
1793 dc->clk, state->pclk, err); in tegra_dc_commit_state()
1796 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), in tegra_dc_commit_state()
1800 if (!dc->soc->has_nvdisplay) { in tegra_dc_commit_state()
1802 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); in tegra_dc_commit_state()
1806 static void tegra_dc_stop(struct tegra_dc *dc) in tegra_dc_stop() argument
1811 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); in tegra_dc_stop()
1813 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); in tegra_dc_stop()
1815 tegra_dc_commit(dc); in tegra_dc_stop()
1818 static bool tegra_dc_idle(struct tegra_dc *dc) in tegra_dc_idle() argument
1822 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND); in tegra_dc_idle()
1827 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout) in tegra_dc_wait_idle() argument
1832 if (tegra_dc_idle(dc)) in tegra_dc_wait_idle()
1838 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n"); in tegra_dc_wait_idle()
1852 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_update_memory_bandwidth() local
1856 if (dc->soc->has_nvdisplay) in tegra_crtc_update_memory_bandwidth()
1891 if (tegra->dc != dc) in tegra_crtc_update_memory_bandwidth()
1942 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_atomic_disable() local
1946 if (!tegra_dc_idle(dc)) { in tegra_crtc_atomic_disable()
1947 tegra_dc_stop(dc); in tegra_crtc_atomic_disable()
1953 tegra_dc_wait_idle(dc, 100); in tegra_crtc_atomic_disable()
1972 if (dc->rgb) { in tegra_crtc_atomic_disable()
1973 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_disable()
1976 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_disable()
1979 tegra_dc_stats_reset(&dc->stats); in tegra_crtc_atomic_disable()
1991 err = host1x_client_suspend(&dc->client); in tegra_crtc_atomic_disable()
1993 dev_err(dc->dev, "failed to suspend: %d\n", err); in tegra_crtc_atomic_disable()
2001 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_atomic_enable() local
2005 err = host1x_client_resume(&dc->client); in tegra_crtc_atomic_enable()
2007 dev_err(dc->dev, "failed to resume: %d\n", err); in tegra_crtc_atomic_enable()
2012 if (dc->syncpt) { in tegra_crtc_atomic_enable()
2013 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable; in tegra_crtc_atomic_enable()
2015 if (dc->soc->has_nvdisplay) in tegra_crtc_atomic_enable()
2021 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); in tegra_crtc_atomic_enable()
2024 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC); in tegra_crtc_atomic_enable()
2027 if (dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
2030 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); in tegra_crtc_atomic_enable()
2037 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); in tegra_crtc_atomic_enable()
2041 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); in tegra_crtc_atomic_enable()
2044 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_crtc_atomic_enable()
2046 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_crtc_atomic_enable()
2050 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); in tegra_crtc_atomic_enable()
2054 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); in tegra_crtc_atomic_enable()
2059 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); in tegra_crtc_atomic_enable()
2063 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); in tegra_crtc_atomic_enable()
2067 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); in tegra_crtc_atomic_enable()
2071 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_crtc_atomic_enable()
2074 if (dc->soc->supports_background_color) in tegra_crtc_atomic_enable()
2075 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR); in tegra_crtc_atomic_enable()
2077 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); in tegra_crtc_atomic_enable()
2080 tegra_dc_commit_state(dc, crtc_state); in tegra_crtc_atomic_enable()
2083 tegra_dc_set_timings(dc, mode); in tegra_crtc_atomic_enable()
2086 if (dc->soc->supports_interlacing) { in tegra_crtc_atomic_enable()
2087 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); in tegra_crtc_atomic_enable()
2089 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); in tegra_crtc_atomic_enable()
2092 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); in tegra_crtc_atomic_enable()
2095 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); in tegra_crtc_atomic_enable()
2097 if (!dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
2098 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_enable()
2101 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_enable()
2105 if (dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
2107 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW); in tegra_crtc_atomic_enable()
2110 tegra_dc_commit(dc); in tegra_crtc_atomic_enable()
2142 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_atomic_flush() local
2146 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
2147 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
2150 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
2151 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
2224 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_calculate_memory_bandwidth() local
2236 if (dc->soc->has_nvdisplay) in tegra_crtc_calculate_memory_bandwidth()
2363 struct tegra_dc *dc = data; in tegra_dc_irq() local
2366 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); in tegra_dc_irq()
2367 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); in tegra_dc_irq()
2373 dc->stats.frames_total++; in tegra_dc_irq()
2374 dc->stats.frames++; in tegra_dc_irq()
2381 drm_crtc_handle_vblank(&dc->base); in tegra_dc_irq()
2382 dc->stats.vblank_total++; in tegra_dc_irq()
2383 dc->stats.vblank++; in tegra_dc_irq()
2390 dc->stats.underflow_total++; in tegra_dc_irq()
2391 dc->stats.underflow++; in tegra_dc_irq()
2398 dc->stats.overflow_total++; in tegra_dc_irq()
2399 dc->stats.overflow++; in tegra_dc_irq()
2403 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__); in tegra_dc_irq()
2404 dc->stats.underflow_total++; in tegra_dc_irq()
2405 dc->stats.underflow++; in tegra_dc_irq()
2411 static bool tegra_dc_has_window_groups(struct tegra_dc *dc) in tegra_dc_has_window_groups() argument
2415 if (!dc->soc->wgrps) in tegra_dc_has_window_groups()
2418 for (i = 0; i < dc->soc->num_wgrps; i++) { in tegra_dc_has_window_groups()
2419 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; in tegra_dc_has_window_groups()
2421 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0) in tegra_dc_has_window_groups()
2442 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_init() local
2452 host1x_syncpt_release_vblank_reservation(client, 26 + dc->pipe); in tegra_dc_init()
2459 if (!tegra_dc_has_window_groups(dc)) in tegra_dc_init()
2468 if (dc->soc->has_nvdisplay) in tegra_dc_init()
2471 dc->syncpt = host1x_syncpt_request(client, flags); in tegra_dc_init()
2472 if (!dc->syncpt) in tegra_dc_init()
2473 dev_warn(dc->dev, "failed to allocate syncpoint\n"); in tegra_dc_init()
2481 if (dc->soc->wgrps) in tegra_dc_init()
2482 primary = tegra_dc_add_shared_planes(drm, dc); in tegra_dc_init()
2484 primary = tegra_dc_add_planes(drm, dc); in tegra_dc_init()
2491 if (dc->soc->supports_cursor) { in tegra_dc_init()
2492 cursor = tegra_dc_cursor_plane_create(drm, dc); in tegra_dc_init()
2499 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true); in tegra_dc_init()
2506 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, in tegra_dc_init()
2511 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); in tegra_dc_init()
2517 if (dc->soc->pitch_align > tegra->pitch_align) in tegra_dc_init()
2518 tegra->pitch_align = dc->soc->pitch_align; in tegra_dc_init()
2521 if (dc->soc->has_nvdisplay) in tegra_dc_init()
2526 err = tegra_dc_rgb_init(drm, dc); in tegra_dc_init()
2528 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); in tegra_dc_init()
2532 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, in tegra_dc_init()
2533 dev_name(dc->dev), dc); in tegra_dc_init()
2535 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, in tegra_dc_init()
2556 host1x_syncpt_put(dc->syncpt); in tegra_dc_init()
2563 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_exit() local
2566 if (!tegra_dc_has_window_groups(dc)) in tegra_dc_exit()
2572 devm_free_irq(dc->dev, dc->irq, dc); in tegra_dc_exit()
2574 err = tegra_dc_rgb_exit(dc); in tegra_dc_exit()
2576 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); in tegra_dc_exit()
2581 host1x_syncpt_put(dc->syncpt); in tegra_dc_exit()
2598 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_runtime_suspend() local
2602 err = reset_control_assert(dc->rst); in tegra_dc_runtime_suspend()
2608 if (dc->soc->has_powergate) in tegra_dc_runtime_suspend()
2609 tegra_powergate_power_off(dc->powergate); in tegra_dc_runtime_suspend()
2611 clk_disable_unprepare(dc->clk); in tegra_dc_runtime_suspend()
2619 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_runtime_resume() local
2629 if (dc->soc->has_powergate) { in tegra_dc_runtime_resume()
2630 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, in tegra_dc_runtime_resume()
2631 dc->rst); in tegra_dc_runtime_resume()
2637 err = clk_prepare_enable(dc->clk); in tegra_dc_runtime_resume()
2643 err = reset_control_deassert(dc->rst); in tegra_dc_runtime_resume()
2653 clk_disable_unprepare(dc->clk); in tegra_dc_runtime_resume()
2781 .dc = 0,
2786 .dc = 1,
2791 .dc = 1,
2796 .dc = 2,
2801 .dc = 2,
2806 .dc = 2,
2831 .dc = 0,
2836 .dc = 1,
2841 .dc = 1,
2846 .dc = 2,
2851 .dc = 2,
2856 .dc = 2,
2906 static int tegra_dc_parse_dt(struct tegra_dc *dc) in tegra_dc_parse_dt() argument
2912 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); in tegra_dc_parse_dt()
2914 dev_err(dc->dev, "missing \"nvidia,head\" property\n"); in tegra_dc_parse_dt()
2929 if (np == dc->dev->of_node) { in tegra_dc_parse_dt()
2938 dc->pipe = value; in tegra_dc_parse_dt()
2945 struct tegra_dc *dc = dev_get_drvdata(dev); in tegra_dc_match_by_pipe() local
2948 return dc->pipe == pipe; in tegra_dc_match_by_pipe()
2951 static int tegra_dc_couple(struct tegra_dc *dc) in tegra_dc_couple() argument
2958 if (dc->soc->coupled_pm && dc->pipe == 1) { in tegra_dc_couple()
2962 companion = driver_find_device(dc->dev->driver, NULL, (const void *)0, in tegra_dc_couple()
2968 dc->client.parent = &parent->client; in tegra_dc_couple()
2970 dev_dbg(dc->dev, "coupled to %s\n", dev_name(companion)); in tegra_dc_couple()
2979 struct tegra_dc *dc; in tegra_dc_probe() local
2988 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); in tegra_dc_probe()
2989 if (!dc) in tegra_dc_probe()
2992 dc->soc = of_device_get_match_data(&pdev->dev); in tegra_dc_probe()
2994 INIT_LIST_HEAD(&dc->list); in tegra_dc_probe()
2995 dc->dev = &pdev->dev; in tegra_dc_probe()
2997 err = tegra_dc_parse_dt(dc); in tegra_dc_probe()
3001 err = tegra_dc_couple(dc); in tegra_dc_probe()
3005 dc->clk = devm_clk_get(&pdev->dev, NULL); in tegra_dc_probe()
3006 if (IS_ERR(dc->clk)) { in tegra_dc_probe()
3008 return PTR_ERR(dc->clk); in tegra_dc_probe()
3011 dc->rst = devm_reset_control_get(&pdev->dev, "dc"); in tegra_dc_probe()
3012 if (IS_ERR(dc->rst)) { in tegra_dc_probe()
3014 return PTR_ERR(dc->rst); in tegra_dc_probe()
3018 err = clk_prepare_enable(dc->clk); in tegra_dc_probe()
3024 err = reset_control_assert(dc->rst); in tegra_dc_probe()
3030 clk_disable_unprepare(dc->clk); in tegra_dc_probe()
3032 if (dc->soc->has_powergate) { in tegra_dc_probe()
3033 if (dc->pipe == 0) in tegra_dc_probe()
3034 dc->powergate = TEGRA_POWERGATE_DIS; in tegra_dc_probe()
3036 dc->powergate = TEGRA_POWERGATE_DISB; in tegra_dc_probe()
3038 tegra_powergate_power_off(dc->powergate); in tegra_dc_probe()
3041 dc->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_dc_probe()
3042 if (IS_ERR(dc->regs)) in tegra_dc_probe()
3043 return PTR_ERR(dc->regs); in tegra_dc_probe()
3045 dc->irq = platform_get_irq(pdev, 0); in tegra_dc_probe()
3046 if (dc->irq < 0) in tegra_dc_probe()
3049 err = tegra_dc_rgb_probe(dc); in tegra_dc_probe()
3056 dev_printk(level, dc->dev, "failed to probe RGB output: %d\n", in tegra_dc_probe()
3061 platform_set_drvdata(pdev, dc); in tegra_dc_probe()
3064 INIT_LIST_HEAD(&dc->client.list); in tegra_dc_probe()
3065 dc->client.ops = &dc_client_ops; in tegra_dc_probe()
3066 dc->client.dev = &pdev->dev; in tegra_dc_probe()
3068 err = host1x_client_register(&dc->client); in tegra_dc_probe()
3079 tegra_dc_rgb_remove(dc); in tegra_dc_probe()
3086 struct tegra_dc *dc = platform_get_drvdata(pdev); in tegra_dc_remove() local
3089 err = host1x_client_unregister(&dc->client); in tegra_dc_remove()
3096 err = tegra_dc_rgb_remove(dc); in tegra_dc_remove()