Lines Matching refs:pll1
37 u32 pll1; member
132 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
147 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
165 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
179 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
193 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
210 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
228 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
247 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
266 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
289 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
307 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
326 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
345 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
817 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1); in tegra_hdmi_setup_tmds()