Lines Matching refs:v3d
153 v3d_has_csd(struct v3d_dev *v3d) in v3d_has_csd() argument
155 return v3d->ver >= 41; in v3d_has_csd()
158 #define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev) argument
162 struct v3d_dev *v3d; member
203 #define V3D_READ(offset) readl(v3d->hub_regs + offset)
204 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset)
206 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset)
207 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset)
209 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset)
210 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset)
212 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset)
213 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset)
220 struct v3d_dev *v3d; member
370 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue);
385 void v3d_reset(struct v3d_dev *v3d);
386 void v3d_invalidate_caches(struct v3d_dev *v3d);
387 void v3d_clean_caches(struct v3d_dev *v3d);
390 int v3d_irq_init(struct v3d_dev *v3d);
391 void v3d_irq_enable(struct v3d_dev *v3d);
392 void v3d_irq_disable(struct v3d_dev *v3d);
393 void v3d_irq_reset(struct v3d_dev *v3d);
398 int v3d_mmu_set_page_table(struct v3d_dev *v3d);
403 int v3d_sched_init(struct v3d_dev *v3d);
404 void v3d_sched_fini(struct v3d_dev *v3d);
409 void v3d_perfmon_start(struct v3d_dev *v3d, struct v3d_perfmon *perfmon);
410 void v3d_perfmon_stop(struct v3d_dev *v3d, struct v3d_perfmon *perfmon,