Lines Matching refs:DRM_DEBUG
391 DRM_DEBUG("surface offset %d > BO size %zd\n", in vc4_full_res_bounds_check()
398 DRM_DEBUG("MSAA tile %d, %d out of bounds " in vc4_full_res_bounds_check()
414 DRM_DEBUG("MSAA surface had nonzero flags/bits\n"); in vc4_rcl_msaa_surface_setup()
428 DRM_DEBUG("MSAA write must be 16b aligned.\n"); in vc4_rcl_msaa_surface_setup()
450 DRM_DEBUG("Extra flags set\n"); in vc4_rcl_surface_setup()
466 DRM_DEBUG("general zs write may not be a full-res.\n"); in vc4_rcl_surface_setup()
471 DRM_DEBUG("load/store general bits set with " in vc4_rcl_surface_setup()
486 DRM_DEBUG("Unknown bits in load/store: 0x%04x\n", in vc4_rcl_surface_setup()
492 DRM_DEBUG("Bad tiling format\n"); in vc4_rcl_surface_setup()
498 DRM_DEBUG("No color format should be set for ZS\n"); in vc4_rcl_surface_setup()
512 DRM_DEBUG("Bad tile buffer format\n"); in vc4_rcl_surface_setup()
516 DRM_DEBUG("Bad load/store buffer %d.\n", buffer); in vc4_rcl_surface_setup()
521 DRM_DEBUG("load/store buffer must be 16b aligned.\n"); in vc4_rcl_surface_setup()
546 DRM_DEBUG("No flags supported on render config.\n"); in vc4_rcl_render_config_surface_setup()
554 DRM_DEBUG("Unknown bits in render config: 0x%04x\n", in vc4_rcl_render_config_surface_setup()
569 DRM_DEBUG("Bad tiling format\n"); in vc4_rcl_render_config_surface_setup()
582 DRM_DEBUG("Bad tile buffer format\n"); in vc4_rcl_render_config_surface_setup()
603 DRM_DEBUG("Bad render tile set (%d,%d)-(%d,%d)\n", in vc4_get_rcl()
612 DRM_DEBUG("Render tiles (%d,%d) outside of bin config " in vc4_get_rcl()
655 DRM_DEBUG("RCL requires color or Z/S write\n"); in vc4_get_rcl()