Lines Matching refs:CHECKREG
13 #define CHECKREG(cval, elem) \ macro
57 CHECKREG(TRCEVENTCTL0R, eventctrl0); in etm4_cfg_map_reg_offset()
58 CHECKREG(TRCEVENTCTL1R, eventctrl1); in etm4_cfg_map_reg_offset()
59 CHECKREG(TRCSTALLCTLR, stall_ctrl); in etm4_cfg_map_reg_offset()
60 CHECKREG(TRCTSCTLR, ts_ctrl); in etm4_cfg_map_reg_offset()
61 CHECKREG(TRCSYNCPR, syncfreq); in etm4_cfg_map_reg_offset()
62 CHECKREG(TRCCCCTLR, ccctlr); in etm4_cfg_map_reg_offset()
63 CHECKREG(TRCBBCTLR, bb_ctrl); in etm4_cfg_map_reg_offset()
64 CHECKREG(TRCVICTLR, vinst_ctrl); in etm4_cfg_map_reg_offset()
65 CHECKREG(TRCVIIECTLR, viiectlr); in etm4_cfg_map_reg_offset()
66 CHECKREG(TRCVISSCTLR, vissctlr); in etm4_cfg_map_reg_offset()
67 CHECKREG(TRCVIPCSSCTLR, vipcssctlr); in etm4_cfg_map_reg_offset()
68 CHECKREG(TRCSEQRSTEVR, seq_rst); in etm4_cfg_map_reg_offset()
69 CHECKREG(TRCSEQSTR, seq_state); in etm4_cfg_map_reg_offset()
70 CHECKREG(TRCEXTINSELR, ext_inp); in etm4_cfg_map_reg_offset()
71 CHECKREG(TRCCIDCCTLR0, ctxid_mask0); in etm4_cfg_map_reg_offset()
72 CHECKREG(TRCCIDCCTLR1, ctxid_mask1); in etm4_cfg_map_reg_offset()
73 CHECKREG(TRCVMIDCCTLR0, vmid_mask0); in etm4_cfg_map_reg_offset()
74 CHECKREG(TRCVMIDCCTLR1, vmid_mask1); in etm4_cfg_map_reg_offset()