Lines Matching refs:aenq
200 struct efa_com_aenq *aenq = &edev->aenq; in efa_com_admin_init_aenq() local
210 size = EFA_ASYNC_QUEUE_DEPTH * sizeof(*aenq->entries); in efa_com_admin_init_aenq()
211 aenq->entries = dma_alloc_coherent(edev->dmadev, size, &aenq->dma_addr, in efa_com_admin_init_aenq()
213 if (!aenq->entries) in efa_com_admin_init_aenq()
216 aenq->aenq_handlers = aenq_handlers; in efa_com_admin_init_aenq()
217 aenq->depth = EFA_ASYNC_QUEUE_DEPTH; in efa_com_admin_init_aenq()
218 aenq->cc = 0; in efa_com_admin_init_aenq()
219 aenq->phase = 1; in efa_com_admin_init_aenq()
221 addr_low = lower_32_bits(aenq->dma_addr); in efa_com_admin_init_aenq()
222 addr_high = upper_32_bits(aenq->dma_addr); in efa_com_admin_init_aenq()
227 EFA_SET(&aenq_caps, EFA_REGS_AENQ_CAPS_AENQ_DEPTH, aenq->depth); in efa_com_admin_init_aenq()
231 aenq->msix_vector_idx); in efa_com_admin_init_aenq()
238 writel(edev->aenq.cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF); in efa_com_admin_init_aenq()
662 struct efa_com_aenq *aenq = &edev->aenq; in efa_com_admin_destroy() local
678 size = aenq->depth * sizeof(*aenq->entries); in efa_com_admin_destroy()
679 dma_free_coherent(edev->dmadev, size, aenq->entries, aenq->dma_addr); in efa_com_admin_destroy()
817 struct efa_aenq_handlers *aenq_handlers = edev->aenq.aenq_handlers; in efa_com_get_specific_aenq_cb()
835 struct efa_com_aenq *aenq = &edev->aenq; in efa_com_aenq_intr_handler() local
842 ci = aenq->cc & (aenq->depth - 1); in efa_com_aenq_intr_handler()
843 phase = aenq->phase; in efa_com_aenq_intr_handler()
844 aenq_e = &aenq->entries[ci]; /* Get first entry */ in efa_com_aenq_intr_handler()
865 if (ci == aenq->depth) { in efa_com_aenq_intr_handler()
869 aenq_e = &aenq->entries[ci]; in efa_com_aenq_intr_handler()
873 aenq->cc += processed; in efa_com_aenq_intr_handler()
874 aenq->phase = phase; in efa_com_aenq_intr_handler()
881 writel(aenq->cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF); in efa_com_aenq_intr_handler()