Lines Matching refs:dd
24 int hfi1_pcie_init(struct hfi1_devdata *dd) in hfi1_pcie_init() argument
27 struct pci_dev *pdev = dd->pcidev; in hfi1_pcie_init()
43 dd_dev_err(dd, "pci enable failed: error %d\n", -ret); in hfi1_pcie_init()
49 dd_dev_err(dd, "pci_request_regions fails: err %d\n", -ret); in hfi1_pcie_init()
62 dd_dev_err(dd, "Unable to set DMA mask: %d\n", ret); in hfi1_pcie_init()
94 int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev) in hfi1_pcie_ddinit() argument
111 dd_dev_err(dd, "chip PIO range does not match\n"); in hfi1_pcie_ddinit()
115 dd->kregbase1 = ioremap(addr, RCV_ARRAY); in hfi1_pcie_ddinit()
116 if (!dd->kregbase1) { in hfi1_pcie_ddinit()
117 dd_dev_err(dd, "UC mapping of kregbase1 failed\n"); in hfi1_pcie_ddinit()
120 dd_dev_info(dd, "UC base1: %p for %x\n", dd->kregbase1, RCV_ARRAY); in hfi1_pcie_ddinit()
123 dd->revision = readq(dd->kregbase1 + CCE_REVISION); in hfi1_pcie_ddinit()
124 if (dd->revision == ~(u64)0) { in hfi1_pcie_ddinit()
125 dd_dev_err(dd, "Cannot read chip CSRs\n"); in hfi1_pcie_ddinit()
129 rcv_array_count = readq(dd->kregbase1 + RCV_ARRAY_CNT); in hfi1_pcie_ddinit()
130 dd_dev_info(dd, "RcvArray count: %u\n", rcv_array_count); in hfi1_pcie_ddinit()
131 dd->base2_start = RCV_ARRAY + rcv_array_count * 8; in hfi1_pcie_ddinit()
133 dd->kregbase2 = ioremap( in hfi1_pcie_ddinit()
134 addr + dd->base2_start, in hfi1_pcie_ddinit()
135 TXE_PIO_SEND - dd->base2_start); in hfi1_pcie_ddinit()
136 if (!dd->kregbase2) { in hfi1_pcie_ddinit()
137 dd_dev_err(dd, "UC mapping of kregbase2 failed\n"); in hfi1_pcie_ddinit()
140 dd_dev_info(dd, "UC base2: %p for %x\n", dd->kregbase2, in hfi1_pcie_ddinit()
141 TXE_PIO_SEND - dd->base2_start); in hfi1_pcie_ddinit()
143 dd->piobase = ioremap_wc(addr + TXE_PIO_SEND, TXE_PIO_SIZE); in hfi1_pcie_ddinit()
144 if (!dd->piobase) { in hfi1_pcie_ddinit()
145 dd_dev_err(dd, "WC mapping of send buffers failed\n"); in hfi1_pcie_ddinit()
148 dd_dev_info(dd, "WC piobase: %p for %x\n", dd->piobase, TXE_PIO_SIZE); in hfi1_pcie_ddinit()
150 dd->physaddr = addr; /* used for io_remap, etc. */ in hfi1_pcie_ddinit()
156 dd->rcvarray_wc = ioremap_wc(addr + RCV_ARRAY, in hfi1_pcie_ddinit()
158 if (!dd->rcvarray_wc) { in hfi1_pcie_ddinit()
159 dd_dev_err(dd, "WC mapping of receive array failed\n"); in hfi1_pcie_ddinit()
162 dd_dev_info(dd, "WC RcvArray: %p for %x\n", in hfi1_pcie_ddinit()
163 dd->rcvarray_wc, rcv_array_count * 8); in hfi1_pcie_ddinit()
165 dd->flags |= HFI1_PRESENT; /* chip.c CSR routines now work */ in hfi1_pcie_ddinit()
169 hfi1_pcie_ddcleanup(dd); in hfi1_pcie_ddinit()
178 void hfi1_pcie_ddcleanup(struct hfi1_devdata *dd) in hfi1_pcie_ddcleanup() argument
180 dd->flags &= ~HFI1_PRESENT; in hfi1_pcie_ddcleanup()
181 if (dd->kregbase1) in hfi1_pcie_ddcleanup()
182 iounmap(dd->kregbase1); in hfi1_pcie_ddcleanup()
183 dd->kregbase1 = NULL; in hfi1_pcie_ddcleanup()
184 if (dd->kregbase2) in hfi1_pcie_ddcleanup()
185 iounmap(dd->kregbase2); in hfi1_pcie_ddcleanup()
186 dd->kregbase2 = NULL; in hfi1_pcie_ddcleanup()
187 if (dd->rcvarray_wc) in hfi1_pcie_ddcleanup()
188 iounmap(dd->rcvarray_wc); in hfi1_pcie_ddcleanup()
189 dd->rcvarray_wc = NULL; in hfi1_pcie_ddcleanup()
190 if (dd->piobase) in hfi1_pcie_ddcleanup()
191 iounmap(dd->piobase); in hfi1_pcie_ddcleanup()
192 dd->piobase = NULL; in hfi1_pcie_ddcleanup()
222 static void update_lbus_info(struct hfi1_devdata *dd) in update_lbus_info() argument
227 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat); in update_lbus_info()
229 dd_dev_err(dd, "Unable to read from PCI config\n"); in update_lbus_info()
233 dd->lbus_width = extract_width(linkstat); in update_lbus_info()
234 dd->lbus_speed = extract_speed(linkstat); in update_lbus_info()
235 snprintf(dd->lbus_info, sizeof(dd->lbus_info), in update_lbus_info()
236 "PCIe,%uMHz,x%u", dd->lbus_speed, dd->lbus_width); in update_lbus_info()
243 int pcie_speeds(struct hfi1_devdata *dd) in pcie_speeds() argument
246 struct pci_dev *parent = dd->pcidev->bus->self; in pcie_speeds()
249 if (!pci_is_pcie(dd->pcidev)) { in pcie_speeds()
250 dd_dev_err(dd, "Can't find PCI Express capability!\n"); in pcie_speeds()
255 dd->link_gen3_capable = 1; in pcie_speeds()
257 ret = pcie_capability_read_dword(dd->pcidev, PCI_EXP_LNKCAP, &linkcap); in pcie_speeds()
259 dd_dev_err(dd, "Unable to read from PCI config\n"); in pcie_speeds()
264 dd_dev_info(dd, in pcie_speeds()
267 dd->link_gen3_capable = 0; in pcie_speeds()
274 (dd->pcidev->bus->max_bus_speed == PCIE_SPEED_2_5GT || in pcie_speeds()
275 dd->pcidev->bus->max_bus_speed == PCIE_SPEED_5_0GT)) { in pcie_speeds()
276 dd_dev_info(dd, "Parent PCIe bridge does not support Gen3\n"); in pcie_speeds()
277 dd->link_gen3_capable = 0; in pcie_speeds()
281 update_lbus_info(dd); in pcie_speeds()
283 dd_dev_info(dd, "%s\n", dd->lbus_info); in pcie_speeds()
293 int restore_pci_variables(struct hfi1_devdata *dd) in restore_pci_variables() argument
297 ret = pci_write_config_word(dd->pcidev, PCI_COMMAND, dd->pci_command); in restore_pci_variables()
301 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, in restore_pci_variables()
302 dd->pcibar0); in restore_pci_variables()
306 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, in restore_pci_variables()
307 dd->pcibar1); in restore_pci_variables()
311 ret = pci_write_config_dword(dd->pcidev, PCI_ROM_ADDRESS, dd->pci_rom); in restore_pci_variables()
315 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, in restore_pci_variables()
316 dd->pcie_devctl); in restore_pci_variables()
320 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL, in restore_pci_variables()
321 dd->pcie_lnkctl); in restore_pci_variables()
325 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL2, in restore_pci_variables()
326 dd->pcie_devctl2); in restore_pci_variables()
330 ret = pci_write_config_dword(dd->pcidev, PCI_CFG_MSIX0, dd->pci_msix0); in restore_pci_variables()
334 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) { in restore_pci_variables()
335 ret = pci_write_config_dword(dd->pcidev, PCIE_CFG_TPH2, in restore_pci_variables()
336 dd->pci_tph2); in restore_pci_variables()
343 dd_dev_err(dd, "Unable to write to PCI config\n"); in restore_pci_variables()
352 int save_pci_variables(struct hfi1_devdata *dd) in save_pci_variables() argument
356 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, in save_pci_variables()
357 &dd->pcibar0); in save_pci_variables()
361 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, in save_pci_variables()
362 &dd->pcibar1); in save_pci_variables()
366 ret = pci_read_config_dword(dd->pcidev, PCI_ROM_ADDRESS, &dd->pci_rom); in save_pci_variables()
370 ret = pci_read_config_word(dd->pcidev, PCI_COMMAND, &dd->pci_command); in save_pci_variables()
374 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, in save_pci_variables()
375 &dd->pcie_devctl); in save_pci_variables()
379 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL, in save_pci_variables()
380 &dd->pcie_lnkctl); in save_pci_variables()
384 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL2, in save_pci_variables()
385 &dd->pcie_devctl2); in save_pci_variables()
389 ret = pci_read_config_dword(dd->pcidev, PCI_CFG_MSIX0, &dd->pci_msix0); in save_pci_variables()
393 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) { in save_pci_variables()
394 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2, in save_pci_variables()
395 &dd->pci_tph2); in save_pci_variables()
402 dd_dev_err(dd, "Unable to read from PCI config\n"); in save_pci_variables()
419 void tune_pcie_caps(struct hfi1_devdata *dd) in tune_pcie_caps() argument
430 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl); in tune_pcie_caps()
432 dd_dev_info(dd, "Enabling PCIe extended tags\n"); in tune_pcie_caps()
434 ret = pcie_capability_write_word(dd->pcidev, in tune_pcie_caps()
437 dd_dev_info(dd, "Unable to write to PCI config\n"); in tune_pcie_caps()
440 parent = dd->pcidev->bus->self; in tune_pcie_caps()
446 dd_dev_info(dd, "Parent not found\n"); in tune_pcie_caps()
450 dd_dev_info(dd, "Parent not root\n"); in tune_pcie_caps()
454 dd_dev_info(dd, "Parent is not PCI Express capable\n"); in tune_pcie_caps()
457 if (!pci_is_pcie(dd->pcidev)) { in tune_pcie_caps()
458 dd_dev_info(dd, "PCI device is not PCI Express capable\n"); in tune_pcie_caps()
464 ep_mpss = dd->pcidev->pcie_mpss; in tune_pcie_caps()
465 ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8; in tune_pcie_caps()
482 pcie_set_mps(dd->pcidev, 128 << ep_mps); in tune_pcie_caps()
496 ep_mrrs = pcie_get_readrq(dd->pcidev); in tune_pcie_caps()
504 pcie_set_readrq(dd->pcidev, ep_mrrs); in tune_pcie_caps()
517 struct hfi1_devdata *dd = pci_get_drvdata(pdev); in pci_error_detected() local
522 dd_dev_info(dd, "State Normal, ignoring\n"); in pci_error_detected()
526 dd_dev_info(dd, "State Frozen, requesting reset\n"); in pci_error_detected()
532 if (dd) { in pci_error_detected()
533 dd_dev_info(dd, "State Permanent Failure, disabling\n"); in pci_error_detected()
535 dd->flags &= ~HFI1_PRESENT; in pci_error_detected()
536 hfi1_disable_after_error(dd); in pci_error_detected()
543 dd_dev_info(dd, "HFI1 PCI errors detected (state %d)\n", in pci_error_detected()
554 struct hfi1_devdata *dd = pci_get_drvdata(pdev); in pci_mmio_enabled() local
557 if (dd && dd->pport) { in pci_mmio_enabled()
558 words = read_port_cntr(dd->pport, C_RX_WORDS, CNTR_INVALID_VL); in pci_mmio_enabled()
561 dd_dev_info(dd, in pci_mmio_enabled()
571 struct hfi1_devdata *dd = pci_get_drvdata(pdev); in pci_slot_reset() local
573 dd_dev_info(dd, "HFI1 slot_reset function called, ignored\n"); in pci_slot_reset()
580 struct hfi1_devdata *dd = pci_get_drvdata(pdev); in pci_resume() local
582 dd_dev_info(dd, "HFI1 resume function called\n"); in pci_resume()
588 hfi1_init(dd, 1); /* same as re-init after reset */ in pci_resume()
725 static int load_eq_table(struct hfi1_devdata *dd, const u8 eq[11][3], u8 fs, in load_eq_table() argument
728 struct pci_dev *pdev = dd->pcidev; in load_eq_table()
745 ret = pci_read_config_dword(dd->pcidev, in load_eq_table()
748 dd_dev_err(dd, "Unable to read from PCI config\n"); in load_eq_table()
756 dd_dev_err(dd, in load_eq_table()
758 dd_dev_err(dd, " prec attn post\n"); in load_eq_table()
760 dd_dev_err(dd, " p%02d: %02x %02x %02x\n", in load_eq_table()
763 dd_dev_err(dd, " %02x %02x %02x\n", in load_eq_table()
778 static void pcie_post_steps(struct hfi1_devdata *dd) in pcie_post_steps() argument
782 set_sbus_fast_mode(dd); in pcie_post_steps()
791 sbus_request(dd, pcie_pcs_addrs[dd->hfi1_id][i], in pcie_post_steps()
795 clear_sbus_fast_mode(dd); in pcie_post_steps()
804 static int trigger_sbr(struct hfi1_devdata *dd) in trigger_sbr() argument
806 struct pci_dev *dev = dd->pcidev; in trigger_sbr()
811 dd_dev_err(dd, "%s: no parent device\n", __func__); in trigger_sbr()
818 dd_dev_err(dd, in trigger_sbr()
835 static void write_gasket_interrupt(struct hfi1_devdata *dd, int index, in write_gasket_interrupt() argument
838 write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (index * 8), in write_gasket_interrupt()
846 static void arm_gasket_logic(struct hfi1_devdata *dd) in arm_gasket_logic() argument
850 reg = (((u64)1 << dd->hfi1_id) << in arm_gasket_logic()
852 ((u64)pcie_serdes_broadcast[dd->hfi1_id] << in arm_gasket_logic()
857 write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg); in arm_gasket_logic()
859 read_csr(dd, ASIC_PCIE_SD_HOST_CMD); in arm_gasket_logic()
881 static void write_xmt_margin(struct hfi1_devdata *dd, const char *fname) in write_xmt_margin() argument
889 pcie_ctrl = read_csr(dd, CCE_PCIE_CTRL); in write_xmt_margin()
899 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL1) { /* integrated */ in write_xmt_margin()
913 if (is_ax(dd)) { in write_xmt_margin()
932 write_csr(dd, CCE_PCIE_CTRL, pcie_ctrl); in write_xmt_margin()
935 dd_dev_dbg(dd, "%s: program XMT margin, CcePcieCtrl 0x%llx\n", in write_xmt_margin()
942 int do_pcie_gen3_transition(struct hfi1_devdata *dd) in do_pcie_gen3_transition() argument
944 struct pci_dev *parent = dd->pcidev->bus->self; in do_pcie_gen3_transition()
964 if (dd->icode != ICODE_RTL_SILICON) in do_pcie_gen3_transition()
978 dd_dev_info(dd, "%s: Skipping PCIe transition\n", __func__); in do_pcie_gen3_transition()
983 if (dd->lbus_speed == target_speed) { in do_pcie_gen3_transition()
984 dd_dev_info(dd, "%s: PCIe already at gen%d, %s\n", __func__, in do_pcie_gen3_transition()
996 dd_dev_info(dd, "%s: No upstream, Can't do gen3 transition\n", in do_pcie_gen3_transition()
1002 target_width = dd->lbus_width; in do_pcie_gen3_transition()
1012 if (pcie_target == 3 && !dd->link_gen3_capable) { in do_pcie_gen3_transition()
1013 dd_dev_err(dd, "The PCIe link is not Gen3 capable\n"); in do_pcie_gen3_transition()
1019 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT); in do_pcie_gen3_transition()
1021 dd_dev_err(dd, "%s: unable to acquire SBus resource\n", in do_pcie_gen3_transition()
1027 therm = read_csr(dd, ASIC_CFG_THERM_POLL_EN); in do_pcie_gen3_transition()
1029 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0); in do_pcie_gen3_transition()
1031 dd_dev_info(dd, "%s: Disabled therm polling\n", in do_pcie_gen3_transition()
1040 dd_dev_info(dd, "%s: downloading firmware\n", __func__); in do_pcie_gen3_transition()
1041 ret = load_pcie_firmware(dd); in do_pcie_gen3_transition()
1049 dd_dev_info(dd, "%s: setting PCIe registers\n", __func__); in do_pcie_gen3_transition()
1059 pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, 0xffff); in do_pcie_gen3_transition()
1070 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32); in do_pcie_gen3_transition()
1080 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32); in do_pcie_gen3_transition()
1090 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0) { /* discrete */ in do_pcie_gen3_transition()
1111 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL101, in do_pcie_gen3_transition()
1116 ret = load_eq_table(dd, eq, fs, div); in do_pcie_gen3_transition()
1128 dd_dev_err(dd, "%s: Invalid Eq Pset %u, setting to %d\n", in do_pcie_gen3_transition()
1132 dd_dev_info(dd, "%s: using EQ Pset %u\n", __func__, pset); in do_pcie_gen3_transition()
1133 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL106, in do_pcie_gen3_transition()
1142 dd_dev_info(dd, "%s: doing pcie post steps\n", __func__); in do_pcie_gen3_transition()
1143 pcie_post_steps(dd); in do_pcie_gen3_transition()
1149 write_gasket_interrupt(dd, intnum++, 0x0006, 0x0050); in do_pcie_gen3_transition()
1152 write_gasket_interrupt(dd, intnum++, 0x0026, in do_pcie_gen3_transition()
1158 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5202); in do_pcie_gen3_transition()
1168 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0200 | pcie_dc); in do_pcie_gen3_transition()
1169 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0100 | pcie_lf); in do_pcie_gen3_transition()
1170 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0000 | pcie_hf); in do_pcie_gen3_transition()
1171 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5500 | pcie_bw); in do_pcie_gen3_transition()
1175 write_gasket_interrupt(dd, intnum++, 0x0000, 0x0000); in do_pcie_gen3_transition()
1180 write_xmt_margin(dd, __func__); in do_pcie_gen3_transition()
1186 dd_dev_info(dd, "%s: clearing ASPM\n", __func__); in do_pcie_gen3_transition()
1187 aspm_hw_disable_l1(dd); in do_pcie_gen3_transition()
1205 dd_dev_info(dd, "%s: setting parent target link speed\n", __func__); in do_pcie_gen3_transition()
1208 dd_dev_err(dd, "Unable to read from PCI config\n"); in do_pcie_gen3_transition()
1213 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, in do_pcie_gen3_transition()
1219 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, in do_pcie_gen3_transition()
1224 dd_dev_err(dd, "Unable to write to PCI config\n"); in do_pcie_gen3_transition()
1229 dd_dev_info(dd, "%s: ..target speed is OK\n", __func__); in do_pcie_gen3_transition()
1232 dd_dev_info(dd, "%s: setting target link speed\n", __func__); in do_pcie_gen3_transition()
1233 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL2, &lnkctl2); in do_pcie_gen3_transition()
1235 dd_dev_err(dd, "Unable to read from PCI config\n"); in do_pcie_gen3_transition()
1240 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, in do_pcie_gen3_transition()
1244 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, in do_pcie_gen3_transition()
1246 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL2, lnkctl2); in do_pcie_gen3_transition()
1248 dd_dev_err(dd, "Unable to write to PCI config\n"); in do_pcie_gen3_transition()
1255 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK); in do_pcie_gen3_transition()
1256 (void)read_csr(dd, CCE_DC_CTRL); /* DC reset hold */ in do_pcie_gen3_transition()
1258 fw_ctrl = read_csr(dd, MISC_CFG_FW_CTRL); in do_pcie_gen3_transition()
1260 dd_dev_info(dd, "%s: arming gasket logic\n", __func__); in do_pcie_gen3_transition()
1261 arm_gasket_logic(dd); in do_pcie_gen3_transition()
1276 dd_dev_info(dd, "%s: calling trigger_sbr\n", __func__); in do_pcie_gen3_transition()
1277 ret = trigger_sbr(dd); in do_pcie_gen3_transition()
1284 ret = pci_read_config_word(dd->pcidev, PCI_VENDOR_ID, &vendor); in do_pcie_gen3_transition()
1286 dd_dev_info(dd, in do_pcie_gen3_transition()
1293 dd_dev_info(dd, "%s: VendorID is all 1s after SBR\n", __func__); in do_pcie_gen3_transition()
1300 dd_dev_info(dd, "%s: calling restore_pci_variables\n", __func__); in do_pcie_gen3_transition()
1301 ret = restore_pci_variables(dd); in do_pcie_gen3_transition()
1303 dd_dev_err(dd, "%s: Could not restore PCI variables\n", in do_pcie_gen3_transition()
1310 write_csr(dd, MISC_CFG_FW_CTRL, fw_ctrl); in do_pcie_gen3_transition()
1322 reg = read_csr(dd, ASIC_PCIE_SD_HOST_STATUS); in do_pcie_gen3_transition()
1323 dd_dev_info(dd, "%s: gasket block status: 0x%llx\n", __func__, reg); in do_pcie_gen3_transition()
1325 dd_dev_err(dd, "SBR failed - unable to read from device\n"); in do_pcie_gen3_transition()
1332 write_csr(dd, CCE_DC_CTRL, 0); in do_pcie_gen3_transition()
1335 setextled(dd, 0); in do_pcie_gen3_transition()
1338 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, ®32); in do_pcie_gen3_transition()
1340 dd_dev_err(dd, "Unable to read from PCI config\n"); in do_pcie_gen3_transition()
1345 dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32); in do_pcie_gen3_transition()
1350 if ((status & (1 << dd->hfi1_id)) == 0) { in do_pcie_gen3_transition()
1351 dd_dev_err(dd, in do_pcie_gen3_transition()
1353 __func__, status, 1 << dd->hfi1_id); in do_pcie_gen3_transition()
1362 dd_dev_err(dd, "%s: gasket error %d\n", __func__, err); in do_pcie_gen3_transition()
1368 update_lbus_info(dd); in do_pcie_gen3_transition()
1369 dd_dev_info(dd, "%s: new speed and width: %s\n", __func__, in do_pcie_gen3_transition()
1370 dd->lbus_info); in do_pcie_gen3_transition()
1372 if (dd->lbus_speed != target_speed || in do_pcie_gen3_transition()
1373 dd->lbus_width < target_width) { /* not target */ in do_pcie_gen3_transition()
1376 dd_dev_err(dd, "PCIe link speed or width did not match target%s\n", in do_pcie_gen3_transition()
1388 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1); in do_pcie_gen3_transition()
1390 dd_dev_info(dd, "%s: Re-enable therm polling\n", in do_pcie_gen3_transition()
1393 release_chip_resource(dd, CR_SBUS); in do_pcie_gen3_transition()
1397 dd_dev_err(dd, "Proceeding at current speed PCIe speed\n"); in do_pcie_gen3_transition()
1401 dd_dev_info(dd, "%s: done\n", __func__); in do_pcie_gen3_transition()