Lines Matching refs:ipcc
83 struct stm32_ipcc *ipcc = data; in stm32_ipcc_rx_irq() local
84 struct device *dev = ipcc->controller.dev; in stm32_ipcc_rx_irq()
90 proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST; in stm32_ipcc_rx_irq()
91 tosr = readl_relaxed(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_rx_irq()
92 mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR); in stm32_ipcc_rx_irq()
97 for (chan = 0; chan < ipcc->n_chans; chan++) { in stm32_ipcc_rx_irq()
103 mbox_chan_received_data(&ipcc->controller.chans[chan], NULL); in stm32_ipcc_rx_irq()
105 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR, in stm32_ipcc_rx_irq()
116 struct stm32_ipcc *ipcc = data; in stm32_ipcc_tx_irq() local
117 struct device *dev = ipcc->controller.dev; in stm32_ipcc_tx_irq()
121 tosr = readl_relaxed(ipcc->reg_proc + IPCC_XTOYSR); in stm32_ipcc_tx_irq()
122 mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR); in stm32_ipcc_tx_irq()
127 for (chan = 0; chan < ipcc->n_chans ; chan++) { in stm32_ipcc_tx_irq()
134 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR, in stm32_ipcc_tx_irq()
137 mbox_chan_txdone(&ipcc->controller.chans[chan], 0); in stm32_ipcc_tx_irq()
148 struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc, in stm32_ipcc_send_data() local
151 dev_dbg(ipcc->controller.dev, "%s: chan:%lu\n", __func__, chan); in stm32_ipcc_send_data()
154 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR, in stm32_ipcc_send_data()
158 stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR, in stm32_ipcc_send_data()
167 struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc, in stm32_ipcc_startup() local
171 ret = clk_prepare_enable(ipcc->clk); in stm32_ipcc_startup()
173 dev_err(ipcc->controller.dev, "can not enable the clock\n"); in stm32_ipcc_startup()
178 stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR, in stm32_ipcc_startup()
187 struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc, in stm32_ipcc_shutdown() local
191 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR, in stm32_ipcc_shutdown()
194 clk_disable_unprepare(ipcc->clk); in stm32_ipcc_shutdown()
207 struct stm32_ipcc *ipcc; in stm32_ipcc_probe() local
219 ipcc = devm_kzalloc(dev, sizeof(*ipcc), GFP_KERNEL); in stm32_ipcc_probe()
220 if (!ipcc) in stm32_ipcc_probe()
223 spin_lock_init(&ipcc->lock); in stm32_ipcc_probe()
226 if (of_property_read_u32(np, "st,proc-id", &ipcc->proc_id)) { in stm32_ipcc_probe()
231 if (ipcc->proc_id >= STM32_MAX_PROCS) { in stm32_ipcc_probe()
232 dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id); in stm32_ipcc_probe()
237 ipcc->reg_base = devm_platform_ioremap_resource(pdev, 0); in stm32_ipcc_probe()
238 if (IS_ERR(ipcc->reg_base)) in stm32_ipcc_probe()
239 return PTR_ERR(ipcc->reg_base); in stm32_ipcc_probe()
241 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; in stm32_ipcc_probe()
244 ipcc->clk = devm_clk_get(dev, NULL); in stm32_ipcc_probe()
245 if (IS_ERR(ipcc->clk)) in stm32_ipcc_probe()
246 return PTR_ERR(ipcc->clk); in stm32_ipcc_probe()
248 ret = clk_prepare_enable(ipcc->clk); in stm32_ipcc_probe()
256 ipcc->irqs[i] = platform_get_irq_byname(pdev, irq_name[i]); in stm32_ipcc_probe()
257 if (ipcc->irqs[i] < 0) { in stm32_ipcc_probe()
258 ret = ipcc->irqs[i]; in stm32_ipcc_probe()
262 ret = devm_request_threaded_irq(dev, ipcc->irqs[i], NULL, in stm32_ipcc_probe()
264 dev_name(dev), ipcc); in stm32_ipcc_probe()
272 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR, in stm32_ipcc_probe()
274 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XCR, in stm32_ipcc_probe()
281 ret = dev_pm_set_wake_irq(dev, ipcc->irqs[IPCC_IRQ_RX]); in stm32_ipcc_probe()
289 ipcc->n_chans = readl_relaxed(ipcc->reg_base + IPCC_HWCFGR); in stm32_ipcc_probe()
290 ipcc->n_chans &= IPCFGR_CHAN_MASK; in stm32_ipcc_probe()
292 ipcc->controller.dev = dev; in stm32_ipcc_probe()
293 ipcc->controller.txdone_irq = true; in stm32_ipcc_probe()
294 ipcc->controller.ops = &stm32_ipcc_ops; in stm32_ipcc_probe()
295 ipcc->controller.num_chans = ipcc->n_chans; in stm32_ipcc_probe()
296 ipcc->controller.chans = devm_kcalloc(dev, ipcc->controller.num_chans, in stm32_ipcc_probe()
297 sizeof(*ipcc->controller.chans), in stm32_ipcc_probe()
299 if (!ipcc->controller.chans) { in stm32_ipcc_probe()
304 for (i = 0; i < ipcc->controller.num_chans; i++) in stm32_ipcc_probe()
305 ipcc->controller.chans[i].con_priv = (void *)i; in stm32_ipcc_probe()
307 ret = devm_mbox_controller_register(dev, &ipcc->controller); in stm32_ipcc_probe()
311 platform_set_drvdata(pdev, ipcc); in stm32_ipcc_probe()
313 ip_ver = readl_relaxed(ipcc->reg_base + IPCC_VER); in stm32_ipcc_probe()
318 ipcc->controller.num_chans, ipcc->proc_id); in stm32_ipcc_probe()
320 clk_disable_unprepare(ipcc->clk); in stm32_ipcc_probe()
329 clk_disable_unprepare(ipcc->clk); in stm32_ipcc_probe()
348 struct stm32_ipcc *ipcc = dev_get_drvdata(dev); in stm32_ipcc_suspend() local
350 ipcc->xmr = readl_relaxed(ipcc->reg_proc + IPCC_XMR); in stm32_ipcc_suspend()
351 ipcc->xcr = readl_relaxed(ipcc->reg_proc + IPCC_XCR); in stm32_ipcc_suspend()
358 struct stm32_ipcc *ipcc = dev_get_drvdata(dev); in stm32_ipcc_resume() local
360 writel_relaxed(ipcc->xmr, ipcc->reg_proc + IPCC_XMR); in stm32_ipcc_resume()
361 writel_relaxed(ipcc->xcr, ipcc->reg_proc + IPCC_XCR); in stm32_ipcc_resume()