Lines Matching refs:smi_write
29 smi_write(MUX_MODE_CTRL, port_mux); in smi_hw_init()
35 smi_write(VIDEO_CTRL_STATUS_A, port_ctrl); in smi_hw_init()
39 smi_write(MPEG2_CTRL_A, port_ctrl); in smi_hw_init()
43 smi_write(VIDEO_CTRL_STATUS_B, port_ctrl); in smi_hw_init()
47 smi_write(MPEG2_CTRL_B, port_ctrl); in smi_hw_init()
50 smi_write(MSI_INT_ENA_CLR, ALL_INT); in smi_hw_init()
52 smi_write(MSI_INT_STATUS_CLR, int_stat); in smi_hw_init()
71 smi_write(sw_ctl, dwCtrl); in smi_i2c_cfg()
75 smi_write(sw_ctl, dwCtrl); in smi_i2c_cfg()
262 smi_write(MSI_INT_ENA_CLR, in smi_port_disableInterrupt()
270 smi_write(MSI_INT_ENA_SET, in smi_port_enableInterrupt()
278 smi_write(MSI_INT_STATUS_CLR, in smi_port_clearInterrupt()
346 smi_write(port->DMA_MANAGEMENT, dmaManagement); in smi_dma_xfer()
792 smi_write(port->DMA_CHAN0_ADDR_LOW, dmaMemPtrLow); in smi_config_DMA()
793 smi_write(port->DMA_CHAN0_ADDR_HI, dmaMemPtrHi); in smi_config_DMA()
794 smi_write(port->DMA_CHAN0_CONTROL, dmaCtlReg); in smi_config_DMA()
807 smi_write(port->DMA_CHAN1_ADDR_LOW, dmaMemPtrLow); in smi_config_DMA()
808 smi_write(port->DMA_CHAN1_ADDR_HI, dmaMemPtrHi); in smi_config_DMA()
809 smi_write(port->DMA_CHAN1_CONTROL, dmaCtlReg); in smi_config_DMA()
825 smi_write(port->DMA_MANAGEMENT, dmaManagement); in smi_start_feed()
1039 smi_write(MSI_INT_ENA_CLR, ALL_INT); in smi_remove()