Lines Matching refs:vr
126 struct viu_reg __iomem *vr; member
242 struct viu_reg __iomem *vr = dev->vr; in viu_start_dma() local
247 iowrite32be(SOFT_RST, &vr->status_cfg); in viu_start_dma()
248 iowrite32be(INT_FIELD_EN, &vr->status_cfg); in viu_start_dma()
253 struct viu_reg __iomem *vr = dev->vr; in viu_stop_dma() local
257 iowrite32be(0, &vr->status_cfg); in viu_stop_dma()
260 status_cfg = ioread32be(&vr->status_cfg); in viu_stop_dma()
262 iowrite32be(status_cfg & 0x3f0000, &vr->status_cfg); in viu_stop_dma()
266 status_cfg = ioread32be(&vr->status_cfg); in viu_stop_dma()
273 iowrite32be(SOFT_RST, &vr->status_cfg); in viu_stop_dma()
274 iowrite32be(0, &vr->status_cfg); in viu_stop_dma()
277 iowrite32be(status_cfg & 0x3f0000, &vr->status_cfg); in viu_stop_dma()
391 struct viu_reg __iomem *vr = dev->vr; in buffer_activate() local
431 iowrite32be(reg_val.dma_inc, &vr->dma_inc); in buffer_activate()
432 iowrite32be(reg_val.picture_count, &vr->picture_count); in buffer_activate()
433 iowrite32be(reg_val.field_base_addr, &vr->field_base_addr); in buffer_activate()
691 inline void viu_activate_overlay(struct viu_reg __iomem *vr) in viu_activate_overlay() argument
693 iowrite32be(reg_val.field_base_addr, &vr->field_base_addr); in viu_activate_overlay()
694 iowrite32be(reg_val.dma_inc, &vr->dma_inc); in viu_activate_overlay()
695 iowrite32be(reg_val.picture_count, &vr->picture_count); in viu_activate_overlay()
774 viu_activate_overlay(dev->vr); in vidioc_overlay()
971 inline void viu_default_settings(struct viu_reg __iomem *vr) in viu_default_settings() argument
973 iowrite32be(0x9512A254, &vr->luminance); in viu_default_settings()
974 iowrite32be(0x03310000, &vr->chroma_r); in viu_default_settings()
975 iowrite32be(0x06600F38, &vr->chroma_g); in viu_default_settings()
976 iowrite32be(0x00000409, &vr->chroma_b); in viu_default_settings()
977 iowrite32be(0x000000ff, &vr->alpha); in viu_default_settings()
978 iowrite32be(0x00000090, &vr->req_alarm); in viu_default_settings()
980 ioread32be(&vr->status_cfg), ioread32be(&vr->field_base_addr)); in viu_default_settings()
985 struct viu_reg __iomem *vr = dev->vr; in viu_overlay_intr() local
998 iowrite32be(addr, &vr->field_base_addr); in viu_overlay_intr()
999 iowrite32be(reg_val.dma_inc, &vr->dma_inc); in viu_overlay_intr()
1002 reg_val.status_cfg, &vr->status_cfg); in viu_overlay_intr()
1006 reg_val.status_cfg, &vr->status_cfg); in viu_overlay_intr()
1014 struct viu_reg __iomem *vr = dev->vr; in viu_capture_intr() local
1052 iowrite32be(addr, &vr->field_base_addr); in viu_capture_intr()
1053 iowrite32be(reg_val.dma_inc, &vr->dma_inc); in viu_capture_intr()
1056 reg_val.status_cfg, &vr->status_cfg); in viu_capture_intr()
1068 (unsigned long)ioread32be(&vr->field_base_addr)); in viu_capture_intr()
1085 struct viu_reg __iomem *vr = dev->vr; in viu_intr() local
1089 status = ioread32be(&vr->status_cfg); in viu_intr()
1099 &vr->status_cfg); in viu_intr()
1128 status = ioread32be(&vr->status_cfg); in viu_intr()
1130 &vr->status_cfg); in viu_intr()
1150 struct viu_reg __iomem *vr; in viu_open() local
1162 vr = dev->vr; in viu_open()
1197 viu_default_settings(vr); in viu_open()
1199 status_cfg = ioread32be(&vr->status_cfg); in viu_open()
1203 &vr->status_cfg); in viu_open()
1205 status_cfg = ioread32be(&vr->status_cfg); in viu_open()
1206 iowrite32be(status_cfg | INT_ALL_STATUS, &vr->status_cfg); in viu_open()
1417 viu_dev->vr = viu_regs; in viu_of_probe()
1499 viu_reset(viu_dev->vr); in viu_of_probe()