Lines Matching refs:writel_relaxed
234 writel_relaxed(bits & ~clr_bits, vfe->base + reg); in vfe_reg_clr()
241 writel_relaxed(bits | set_bits, vfe->base + reg); in vfe_reg_set()
256 writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD); in vfe_global_reset()
261 writel_relaxed(VFE_0_BUS_BDG_CMD_HALT_REQ, in vfe_halt_request()
267 writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD); in vfe_halt_clear()
319 writel_relaxed(reg, vfe->base + in vfe_wm_line_based()
328 writel_relaxed(reg, vfe->base + in vfe_wm_line_based()
331 writel_relaxed(0, vfe->base + in vfe_wm_line_based()
333 writel_relaxed(0, vfe->base + in vfe_wm_line_based()
350 writel_relaxed(reg, in vfe_wm_set_framedrop_period()
357 writel_relaxed(pattern, in vfe_wm_set_framedrop_pattern()
368 writel_relaxed(reg, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(wm)); in vfe_wm_set_ub_cfg()
374 writel_relaxed(VFE_0_BUS_CMD_Mx_RLD_CMD(wm), vfe->base + VFE_0_BUS_CMD); in vfe_bus_reload_wm()
380 writel_relaxed(addr, in vfe_wm_set_ping_addr()
386 writel_relaxed(addr, in vfe_wm_set_pong_addr()
402 writel_relaxed(0x10000009, vfe->base + VFE_0_BUS_CFG); in vfe_bus_enable_wr_if()
404 writel_relaxed(0, vfe->base + VFE_0_BUS_CFG); in vfe_bus_enable_wr_if()
445 writel_relaxed(VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF, in vfe_wm_set_subsample()
536 writel_relaxed(vfe->reg_update, vfe->base + VFE_0_REG_UPDATE); in vfe_reg_update()
608 writel_relaxed(VFE_0_DEMUX_CFG_PERIOD, vfe->base + VFE_0_DEMUX_CFG); in vfe_set_demux_cfg()
611 writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_0); in vfe_set_demux_cfg()
614 writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_1); in vfe_set_demux_cfg()
636 writel_relaxed(even_cfg, vfe->base + VFE_0_DEMUX_EVEN_CFG); in vfe_set_demux_cfg()
637 writel_relaxed(odd_cfg, vfe->base + VFE_0_DEMUX_ODD_CFG); in vfe_set_demux_cfg()
648 writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG); in vfe_set_scale_cfg()
653 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE); in vfe_set_scale_cfg()
658 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_PHASE); in vfe_set_scale_cfg()
663 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE); in vfe_set_scale_cfg()
668 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_PHASE); in vfe_set_scale_cfg()
670 writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG); in vfe_set_scale_cfg()
675 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE); in vfe_set_scale_cfg()
680 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE); in vfe_set_scale_cfg()
687 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE); in vfe_set_scale_cfg()
692 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE); in vfe_set_scale_cfg()
704 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_WIDTH); in vfe_set_crop_cfg()
709 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_HEIGHT); in vfe_set_crop_cfg()
714 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_WIDTH); in vfe_set_crop_cfg()
723 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_HEIGHT); in vfe_set_crop_cfg()
732 writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MAX_CFG); in vfe_set_clamp_cfg()
738 writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MIN_CFG); in vfe_set_clamp_cfg()
746 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0); in vfe_set_qos()
747 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1); in vfe_set_qos()
748 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2); in vfe_set_qos()
749 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3); in vfe_set_qos()
750 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4); in vfe_set_qos()
751 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5); in vfe_set_qos()
752 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6); in vfe_set_qos()
753 writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7); in vfe_set_qos()
793 writel_relaxed(val, vfe->base + VFE_0_CORE_CFG); in vfe_set_camif_cfg()
797 writel_relaxed(val, vfe->base + VFE_0_CAMIF_FRAME_CFG); in vfe_set_camif_cfg()
800 writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_WIDTH_CFG); in vfe_set_camif_cfg()
803 writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_HEIGHT_CFG); in vfe_set_camif_cfg()
806 writel_relaxed(val, vfe->base + VFE_0_CAMIF_SUBSAMPLE_CFG_0); in vfe_set_camif_cfg()
809 writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN); in vfe_set_camif_cfg()
815 writel_relaxed(val, vfe->base + VFE_0_CAMIF_CFG); in vfe_set_camif_cfg()
823 writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); in vfe_set_camif_cmd()
831 writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); in vfe_set_camif_cmd()
842 writel_relaxed(val, vfe->base + VFE_0_MODULE_CFG); in vfe_set_module_cfg()
844 writel_relaxed(0x0, vfe->base + VFE_0_MODULE_CFG); in vfe_set_module_cfg()
868 writel_relaxed(*value0, vfe->base + VFE_0_IRQ_CLEAR_0); in vfe_isr_read()
869 writel_relaxed(*value1, vfe->base + VFE_0_IRQ_CLEAR_1); in vfe_isr_read()
872 writel_relaxed(VFE_0_IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_0_IRQ_CMD); in vfe_isr_read()