Lines Matching refs:mc_readl
286 value = mc_readl(mc, rst->reset); in tegra20_mc_hotreset_assert()
302 value = mc_readl(mc, rst->reset); in tegra20_mc_hotreset_deassert()
318 value = mc_readl(mc, rst->control) & ~BIT(rst->bit); in tegra20_mc_block_dma()
329 return mc_readl(mc, rst->status) == 0; in tegra20_mc_dma_idling()
335 return (mc_readl(mc, rst->reset) & BIT(rst->bit)) == 0; in tegra20_mc_reset_status()
346 value = mc_readl(mc, rst->control) | BIT(rst->bit); in tegra20_mc_unblock_dma()
469 count0 = mc_readl(mc, MC_STAT_EMC_COUNT_0); in tegra20_mc_stat_gather()
470 count1 = mc_readl(mc, MC_STAT_EMC_COUNT_1); in tegra20_mc_stat_gather()
471 clocks = mc_readl(mc, MC_STAT_EMC_CLOCKS); in tegra20_mc_stat_gather()
723 status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; in tegra20_mc_handle_irq()
738 value = mc_readl(mc, reg); in tegra20_mc_handle_irq()
749 value = mc_readl(mc, reg); in tegra20_mc_handle_irq()
760 value = mc_readl(mc, reg); in tegra20_mc_handle_irq()
776 addr = mc_readl(mc, reg + sizeof(u32)); in tegra20_mc_handle_irq()