Lines Matching refs:INFO
20 #define INFO (1 << 0) macro
624 emc_dbg(emc, INFO, "Running clock change.\n"); in tegra210_emc_r21021_set_clock()
675 emc_dbg(emc, INFO, "Clock change version: %d\n", in tegra210_emc_r21021_set_clock()
677 emc_dbg(emc, INFO, "DRAM type = %d\n", dram_type); in tegra210_emc_r21021_set_clock()
678 emc_dbg(emc, INFO, "DRAM dev #: %u\n", emc->num_devices); in tegra210_emc_r21021_set_clock()
679 emc_dbg(emc, INFO, "Next EMC clksrc: 0x%08x\n", clksrc); in tegra210_emc_r21021_set_clock()
680 emc_dbg(emc, INFO, "DLL clksrc: 0x%08x\n", next->dll_clk_src); in tegra210_emc_r21021_set_clock()
681 emc_dbg(emc, INFO, "last rate: %u, next rate %u\n", last->rate, in tegra210_emc_r21021_set_clock()
683 emc_dbg(emc, INFO, "last period: %u, next period: %u\n", in tegra210_emc_r21021_set_clock()
685 emc_dbg(emc, INFO, " shared_zq_resistor: %d\n", !!shared_zq_resistor); in tegra210_emc_r21021_set_clock()
686 emc_dbg(emc, INFO, " num_channels: %u\n", emc->num_channels); in tegra210_emc_r21021_set_clock()
687 emc_dbg(emc, INFO, " opt_dll_mode: %d\n", opt_dll_mode); in tegra210_emc_r21021_set_clock()
829 emc_dbg(emc, INFO, "Prelock enabled for target frequency.\n"); in tegra210_emc_r21021_set_clock()
831 emc_dbg(emc, INFO, "DLL out: 0x%03x\n", value); in tegra210_emc_r21021_set_clock()
833 emc_dbg(emc, INFO, "Disabling DLL for target frequency.\n"); in tegra210_emc_r21021_set_clock()
929 emc_dbg(emc, INFO, "tRTM = %u, EMC_RP = %u\n", tRTM, in tegra210_emc_r21021_set_clock()
980 emc_dbg(emc, INFO, "Skipped WAR\n"); in tegra210_emc_r21021_set_clock()
1419 emc_dbg(emc, INFO, "tZQCAL_lpddr4_fc_adj = %u\n", tZQCAL_lpddr4_fc_adj); in tegra210_emc_r21021_set_clock()
1420 emc_dbg(emc, INFO, "dst_clk_period = %u\n", in tegra210_emc_r21021_set_clock()
1422 emc_dbg(emc, INFO, "next->dram_timings[T_PDEX] = %u\n", in tegra210_emc_r21021_set_clock()
1424 emc_dbg(emc, INFO, "zq_latch_dvfs_wait_time = %d\n", in tegra210_emc_r21021_set_clock()